JP2008510320A - Gradient semiconductor layer - Google Patents

Gradient semiconductor layer Download PDF

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JP2008510320A
JP2008510320A JP2007527945A JP2007527945A JP2008510320A JP 2008510320 A JP2008510320 A JP 2008510320A JP 2007527945 A JP2007527945 A JP 2007527945A JP 2007527945 A JP2007527945 A JP 2007527945A JP 2008510320 A JP2008510320 A JP 2008510320A
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semiconductor layer
germanium
layer
concentration
silicon
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ジー． サダカ、マリアム
ジー． トーマス、ショーン
アール． ホワイト、テッド
リュウ、チュン−リ
エル． バール、アレクサンダー
ニューエン、ビック−イェン
シーン、ブーン−ユウ
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NXP USA Inc
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

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Abstract

半導体装置を形成するプロセス。プロセスは、ストレインドシリコン層（３０５）を形成するためにテンプレート層（２０７）を形成することを含む。１例では、下部ではゲルマニウムの濃度がより高く、上部ではゲルマニウムの濃度がより低い、勾配シリコンゲルマニウム層（１０７）が形成される。凝縮プロセスを受けると、層の上部のゲルマニウムは、シリコンゲルマニウム層の残りの部分に拡散する。シリコンゲルマニウム層は下部でゲルマニウムの濃度がより高いため、シリコンゲルマニウム層の残りの部分の上部では凝縮後のゲルマニウムの集積が低減され得る。A process for forming a semiconductor device. The process includes forming a template layer (207) to form a strained silicon layer (305). In one example, a gradient silicon germanium layer (107) is formed with a higher germanium concentration at the bottom and a lower germanium concentration at the top. Upon undergoing the condensation process, the germanium on top of the layer diffuses into the rest of the silicon germanium layer. Since the silicon germanium layer has a higher germanium concentration in the lower part, the accumulation of germanium after condensation can be reduced in the upper part of the remaining part of the silicon germanium layer.

Description

本発明は、一般に半導体装置に関し、詳細にはストレインドチャネル領域を備えた半導体装置の形成に関する。   The present invention generally relates to semiconductor devices, and more particularly to the formation of semiconductor devices with strained channel regions.

電子と正孔の運動性は、特にセミコンダクター・オン・インシュレータ構成（ＳＯＩ）を有するウエハから構築された装置に関しては、チャネル領域への（例えば２軸の引張歪みによる）ストレインドシリコンの利用により増強され得る。ストレインドシリコン層は、テンプレート層（例えばシリコンゲルマニウム）にシリコン層を堆積させることにより形成され得る。いくつかのプロセスでは、シリコンの堆積前にシリコンゲルマニウムテンプレート層を弛緩するために、テンプレート層に対して凝縮プロセスが行なわれる。そのような凝縮プロセスの１例は、シリコンゲルマニウムテンプレート層の酸化を含む。そのようなプロセスにより、テンプレート層の上にはＳｉＯ2の層が成長すると共に、テンプレート層の消費された部分のゲルマニウムがシリコンゲルマニウム層の残りの部分へと下方に拡散し、残りの部分を濃縮する。続いて、ストレインドシリコンを堆積させる前に、その酸化物はエッチング除去される。 Electron and hole motility is enhanced by the use of strained silicon (eg, due to biaxial tensile strain) in the channel region, especially for devices constructed from wafers with a semiconductor-on-insulator configuration (SOI) Can be done. The strained silicon layer can be formed by depositing a silicon layer on a template layer (eg, silicon germanium). In some processes, a condensation process is performed on the template layer to relax the silicon germanium template layer prior to silicon deposition. One example of such a condensation process involves the oxidation of a silicon germanium template layer. With such a process, a layer of SiO 2 is grown on the template layer, and the consumed portion of germanium diffuses downward into the remaining portion of the silicon germanium layer, concentrating the remaining portion. To do. Subsequently, the oxide is etched away before the strained silicon is deposited.

そのような方法で生じ得る１つの問題は、シリコンゲルマニウム層の残りの部分にゲルマニウムが十分に拡散しない恐れがあるということである。従って、残りの層の上部におけるゲルマニウムの濃度がシリコンゲルマニウム層の下部のゲルマニウム濃度に対して相対的に高い場合がある。テンプレート層中のゲルマニウム濃度のこのような差は転位を引き起こし、これは転位領域に形成された半導体装置の機能不全につながり得る。   One problem that can arise with such a method is that germanium may not diffuse sufficiently into the rest of the silicon germanium layer. Therefore, the germanium concentration in the upper part of the remaining layer may be relatively higher than the germanium concentration in the lower part of the silicon germanium layer. Such a difference in the germanium concentration in the template layer causes dislocation, which can lead to malfunction of the semiconductor device formed in the dislocation region.

半導体装置製造の改良されたプロセスが必要とされている。   There is a need for improved processes for semiconductor device manufacturing.

添付図面を参照すれば、本発明は一層よく理解され、また、本発明の多くの目的、特徴、および利点が当業者には明らかになるであろう。
特段の注意がない限り、異なる図面中の同じ参照符号の使用は同一の部材を示す。図は必ずしも正しい縮尺で描かれているわけではない。 The present invention is better understood and the many objects, features and advantages of the present invention will become apparent to those skilled in the art with reference to the accompanying drawings.
Unless otherwise noted, the use of the same reference symbols in different drawings indicates the same component. The figures are not necessarily drawn to scale.

以下に、本発明を実施するための態様の詳細な説明を述べる。この記述は本発明を例証するものであって、限定とみなされるべきではない。
ゲルマニウムを勾配濃度にしたテンプレート層材料の層を提供することにより、凝縮プロセスが該層に行なわれた後、より勾配が一様なゲルマニウムが与えられることが見出された。 Hereinafter, a detailed description of embodiments for carrying out the present invention will be described. This description is illustrative of the invention and is not to be considered as limiting.
It has been found that providing a layer of germanium-graded template layer material provides a more uniform germanium after the condensation process has been performed on the layer.

図１は、半導体装置の製造中のある段階にあるウエハ１０１の部分断面図である。示された実施形態では、ウエハ１０１は、半導体基板１０３と、基板１０３上に配置された絶縁層１０５（例えば酸化物）とを備えている。絶縁層１０５の上にはシリコン層１０６（例えば１００オングストローム）が配置される。１実施形態では、層１０６、層１０５および基板１０３は、ＳＥＶＩＯＸプロセスにより、または別のウエハの酸化物層上に１つのシリコンウエハを接合することにより、形成される。示された実施形態では、ウエハ１０１は絶縁体の上に半導体がある（セミコンダクター・オン・インシュレータ，ＳＯＩ）の構成を有している。別の実施形態では、ウエハ１０１は別のタイプのＳＯＩ構成（例えばシリコン・オン・サファイアまたはシリコン・オン・クオーツ）を有してもよい。   FIG. 1 is a partial cross-sectional view of a wafer 101 at a stage during manufacturing of a semiconductor device. In the illustrated embodiment, the wafer 101 includes a semiconductor substrate 103 and an insulating layer 105 (eg, oxide) disposed on the substrate 103. A silicon layer 106 (for example, 100 Å) is disposed on the insulating layer 105. In one embodiment, layer 106, layer 105, and substrate 103 are formed by a SEVIOX process or by bonding one silicon wafer onto an oxide layer of another wafer. In the embodiment shown, the wafer 101 has a configuration in which a semiconductor is on an insulator (semiconductor on insulator, SOI). In other embodiments, the wafer 101 may have another type of SOI configuration (eg, silicon on sapphire or silicon on quartz).

示された実施形態では、シリコン層１０６の上にシリコンゲルマニウム層１０７が形成される。示された実施形態では、層１０７のゲルマニウム濃度は、層１０７の下部の高濃度から層１０７の上部のより低い濃度まで勾配をつけられている。   In the illustrated embodiment, a silicon germanium layer 107 is formed on the silicon layer 106. In the illustrated embodiment, the germanium concentration of layer 107 is graded from a high concentration at the bottom of layer 107 to a lower concentration at the top of layer 107.

１実施形態では、層１０７は、化学蒸着（ＣＶＤ）プロセスによりエピタキシ成長させられる。そのようなプロセスの１つの例では、ゲルマニウム含有ガス（例えばゲルマンまたは四塩化ゲルマニウム）およびシリコン含有ガス（例えばシランまたは二塩化ジクロロシラン）が、ゲルマニウムガス対シリコン含有ガスの第１の比で、層１０６の上にわたって流される。層１０７のより高い部分が形成されるにつれて、ゲルマニウムガスとシリコン含有ガスの比は小さくされ、それらの部分のゲルマニウム濃度は低減される。   In one embodiment, layer 107 is epitaxially grown by a chemical vapor deposition (CVD) process. In one example of such a process, a germanium-containing gas (eg, germane or germanium tetrachloride) and a silicon-containing gas (eg, silane or dichlorosilane dichloride) are layered at a first ratio of germanium gas to silicon-containing gas. Is flowed over 106. As higher portions of layer 107 are formed, the ratio of germanium gas to silicon-containing gas is reduced and the germanium concentration in those portions is reduced.

１例において、ゲルマニウムの濃度は層１０７の底部では５０％であり、層１０７の上部では１０％まで徐々に減少される。しかしながら、他の実施形態は他のゲルマニウム勾配分布を有していてもよい。別の実施形態では、層１０７の底部のゲルマニウムの濃度が１００％ゲルマニウムから１０％ゲルマニウムまでの範囲であり、層１０７の上部のゲルマニウム濃度は０−２０％の範囲であり得る。しかしながら、別の実施形態では、層１０７は上部と底部の両方で異なるゲルマニウム濃度を有してもよい。   In one example, the germanium concentration is 50% at the bottom of layer 107 and gradually decreases to 10% at the top of layer 107. However, other embodiments may have other germanium gradient distributions. In another embodiment, the concentration of germanium at the bottom of layer 107 can range from 100% germanium to 10% germanium, and the germanium concentration at the top of layer 107 can range from 0-20%. However, in another embodiment, layer 107 may have different germanium concentrations at both the top and bottom.

１実施形態では、層１０７は、厚さが７００オングストロームであり、底部の３０％から上部の１０％までのゲルマニウム勾配を備えている。別の実施形態では、層１０７は別の厚さであってもよい。いくつかの実施形態では、層１０７の厚さは、層１０７の底部のゲルマニウム濃度および層１０７の上部のゲルマニウム濃度ならびにＣＶＤプロセス中のゲルマニウム濃度変更能に依存して決定される。   In one embodiment, layer 107 is 700 angstroms thick and comprises a germanium gradient from 30% at the bottom to 10% at the top. In other embodiments, layer 107 may have other thicknesses. In some embodiments, the thickness of layer 107 is determined depending on the germanium concentration at the bottom of layer 107 and the germanium concentration at the top of layer 107 and the ability to change the germanium concentration during the CVD process.

示された実施形態では、層１０７のゲルマニウム濃度は、上部が下部よりも低いゲルマニウム濃度を有するという点で、戻り方向に勾配するものであることを特徴とする。しかしながら、いくつかの実施形態では、層１０７は、ゲルマニウム濃度が戻り方向に勾配しない部分を含んでもよい。例えば、１実施形態では、層１０７が絶縁層１０５の上に形成され、最初はゲルマニウム濃度が０であるが急速に増大する（例えば３０％）ようにしてもよい。その後、この上側部分のゲルマニウム濃度は、上部でより低い濃度に（例えば１０％）に戻り方向に勾配するだろう。   In the embodiment shown, the germanium concentration of layer 107 is characterized by a gradient in the return direction in that the upper portion has a lower germanium concentration than the lower portion. However, in some embodiments, layer 107 may include portions where the germanium concentration does not slope in the return direction. For example, in one embodiment, the layer 107 may be formed on the insulating layer 105, initially having a germanium concentration of 0 but increasing rapidly (eg, 30%). The germanium concentration in this upper part will then slope back to a lower concentration (eg 10%) at the top.

いくつかの実施形態では、ＣＶＤプロセスにおけるゲルマニウム含有ガス対シリコン含有ガスの比は、直線的にまたは段階的な様式で調節され得る。いくつかの実施形態では、段階的な様式のプロセスのステップ数は、ゲルマニウム濃度の所望の変化に依存して決定される。   In some embodiments, the ratio of germanium-containing gas to silicon-containing gas in the CVD process can be adjusted in a linear or stepwise fashion. In some embodiments, the number of steps in a stepwise manner process is determined depending on the desired change in germanium concentration.

図２は、凝縮プロセスがウエハ１０１に対して行なわれた後のウエハ１０１の部分断面図を示す。示された実施形態に対する凝縮プロセスの間、層１０７（図１を参照）の上部は消費され、シリコンゲルマニウム層の残りの部分２０７の上に酸化シリコン層２０９が成長する。また、凝縮プロセスの間に、層１０６が層１０７の残りの部分と効果的に合一するように、層１０７からのゲルマニウムが層１０６に拡散する。従って、図２では、層２０７は層１０６と層１０７の残りの部分との両方を含んでいる。別の実施形態では、層の残りの部分のゲルマニウム濃度を増加させる別のタイプの凝縮操作が利用されてもよい。   FIG. 2 shows a partial cross-sectional view of wafer 101 after the condensation process has been performed on wafer 101. During the condensation process for the illustrated embodiment, the top of layer 107 (see FIG. 1) is consumed and a silicon oxide layer 209 is grown on the remaining portion 207 of the silicon germanium layer. Also, germanium from layer 107 diffuses into layer 106 such that layer 106 effectively coalesces with the rest of layer 107 during the condensation process. Thus, in FIG. 2, layer 207 includes both layer 106 and the rest of layer 107. In another embodiment, another type of condensation operation that increases the germanium concentration in the remainder of the layer may be utilized.

凝縮プロセスの間、層１０７の消費された上部のゲルマニウムは、残りの部分（層２０７）に拡散する。層１０７は勾配しているため、層２０７中のゲルマニウム濃度は凝縮プロセス後は比較的一様である。いくつかの先行技術のプロセスと比較して、層２０７の上部ではゲルマニウム増強の相対的な不足がある。１実施形態では、層２０７のゲルマニウム濃度は、層２０７の厚さにわたって約３５％±２％である。しかしながら、結果として得られる層２０７のゲルマニウム濃度は、別の実施形態では別の値であってもよいし、および／または別の勾配を有していてもよい。   During the condensation process, the spent upper germanium of layer 107 diffuses into the rest (layer 207). Because layer 107 is gradient, the germanium concentration in layer 207 is relatively uniform after the condensation process. Compared to some prior art processes, there is a relative lack of germanium enhancement at the top of layer 207. In one embodiment, the germanium concentration of layer 207 is about 35% ± 2% over the thickness of layer 207. However, the germanium concentration of the resulting layer 207 may have a different value and / or have a different slope in other embodiments.

１実施形態では、凝縮プロセスは、６％ ＨＣＬガス（例えば６％濃度で）で３０分間、１０５０℃で行なわれる。しかしながら、他の温度（１２００℃以内およびそれより高い温度）で、他の時間で、および／または他のガスの存在下で、別の凝縮プロセスが行われてもよい。１実施形態では、層２０７は４０ｎｍの厚さを有している。   In one embodiment, the condensation process is performed at 1050 ° C. for 30 minutes with 6% HCL gas (eg, at 6% concentration). However, other condensation processes may be performed at other temperatures (within 1200 ° C. and higher), at other times, and / or in the presence of other gases. In one embodiment, layer 207 has a thickness of 40 nm.

異なる濃度のシリコンゲルマニウムを使用することの別の利点は、低温（例えばいくつかの例では１２００℃のプロセスに対して１０５０℃）および／またはより短い凝縮時間での凝縮プロセスが可能となり得ることである。１実施形態では、層１０７の底部のゲルマニウム濃度をより高くすると、拡散の第２の駆動力が提供され、より高い部分ではゲルマニウム濃度がより低いため、ゲルマニウム原子は層１０７内を上方に拡散する。この拡散のための第２の駆動力は、層１０７の上部におけるゲルマニウムからのゲルマニウムの拡散の駆動力に加えて、凝縮により消費される。低温で凝縮プロセスを行なうことの１つの利点は、それが層２０７で生じる恐れのある融解を回避し得ることである。いくつかの実施形態では、ゲルマニウムの濃度がより高いと、シリコンゲルマニウムの融点が低下する。したがって、低温で凝縮プロセスを行なう能力は有益であり得る。   Another advantage of using different concentrations of silicon germanium is that it may allow condensation processes at low temperatures (eg, 1050 ° C. for 1200 ° C. in some examples) and / or shorter condensation times. is there. In one embodiment, a higher germanium concentration at the bottom of layer 107 provides a second driving force for diffusion, and germanium atoms diffuse upward in layer 107 because the higher portion has a lower germanium concentration. . The second driving force for this diffusion is consumed by condensation in addition to the driving force for the diffusion of germanium from germanium at the top of layer 107. One advantage of performing the condensation process at low temperature is that it can avoid melting that may occur in layer 207. In some embodiments, the higher the concentration of germanium, the lower the melting point of silicon germanium. Thus, the ability to perform a condensation process at low temperatures can be beneficial.

いくつかの実施形態では、シリコンゲルマニウム層１０７の凝縮前に、層１０７の上にシリコンキャップ層（図示しない）が形成され得る。
図３は、酸化物層２０９が除去され（例えばＨＦウェットエッチングにより）、ストレインドシリコン層３０５がシリコンゲルマニウム層２０７にエピタキシ堆積させられた後の、ウエハ１０１の部分断面図である。層２０７は層３０５を堆積させるためのテンプレート層として機能し、層３０５の格子は通常層２０７の格子と同じ格子定数を有する。１実施形態では、層３０５は２００オングストロームの厚さを有するが、別の実施形態では別の厚さを有してもよい。 In some embodiments, a silicon cap layer (not shown) may be formed on layer 107 prior to condensation of silicon germanium layer 107.
FIG. 3 is a partial cross-sectional view of wafer 101 after oxide layer 209 has been removed (eg, by HF wet etching) and strained silicon layer 305 has been epitaxially deposited on silicon germanium layer 207. The layer 207 functions as a template layer for depositing the layer 305, and the lattice of the layer 305 has the same lattice constant as the lattice of the normal layer 207. In one embodiment, layer 305 has a thickness of 200 angstroms, but in other embodiments it may have a different thickness.

１実施形態では、層２０７は凝縮プロセスの後に弛緩される。従って、シリコン層３０５の格子は層２０７の格子定数と一致させるための引張歪みを有する。別の実施形態では、層２０７は別の歪み特性（例えば部分的に弛緩されている）を有してもよい。層２０７の歪み特性は、層１０７の歪み濃度よりも弛緩される。   In one embodiment, layer 207 is relaxed after the condensation process. Accordingly, the lattice of the silicon layer 305 has a tensile strain to match the lattice constant of the layer 207. In other embodiments, layer 207 may have other strain characteristics (eg, partially relaxed). The strain characteristics of the layer 207 are more relaxed than the strain concentration of the layer 107.

いくつかの実施形態では、発明の名称が「テンプレート層生成（Template Layer Formation）」である、同一出願人により同時出願された整理番号ＳＣ１２８５１ＺＰ Ｐ０１の出願に記載されたプロセスを含む、別のプロセスが層３０５に行なわれてもよい。この出願全体は参照により本明細書に組み込まれる。さらなるプロセスの例には、塩素系ガスによるポストベーキングが含まれる。   In some embodiments, another process comprises the process described in the application of serial number SC12851ZP P01 filed concurrently with the same applicant, whose title is “Template Layer Formation”. It may be performed on layer 305. This entire application is incorporated herein by reference. Examples of further processes include post baking with chlorinated gases.

図４は、トランジスタ４０１の生成後のウエハ１０１の部分断面図を示す。トランジスタ４０１は、ゲート酸化物４０７上に形成されたゲート４０３を有する。ゲート酸化物４０７はストレインシリコン層３０５上に形成される。トランジスタ３０７は、層３０５の上方に形成されたスペーサ４０５をさらに有する。示された実施形態では、トランジスタ４０１は、例えば選択領域で層３０５および２０７にドーパントを注入することにより形成されたソース／ドレイン領域４１１および４０９を有する。トランジスタ４０１は、（示された実施形態では）ストレインドシリコン層３０５に形成されたチャネル領域４１３を有する。   FIG. 4 shows a partial cross-sectional view of the wafer 101 after the transistor 401 is generated. Transistor 401 has a gate 403 formed on gate oxide 407. A gate oxide 407 is formed on the strain silicon layer 305. The transistor 307 further includes a spacer 405 formed above the layer 305. In the illustrated embodiment, transistor 401 has source / drain regions 411 and 409 formed, for example, by implanting dopants into layers 305 and 207 in selected regions. The transistor 401 has a channel region 413 formed in the strained silicon layer 305 (in the illustrated embodiment).

別の実施形態では、テンプレート層材料は、シリコンゲルマニウム炭素、シリコンスズおよびゲルマニウム炭素中の炭素のような他の成分を含んでもよい。ウエハ１０１は他のトランジスタ（図示しない）を備えていてもよい。いくつかの実施形態では、層１０７がいくつかのウエハ１０１の領域に選択的に形成され得る。別の実施形態では、層１０７が全部のウエハ１０１の上に形成される。また、いくつかの実施形態では、凝縮プロセスが全部の層１０７に選択的に行なわれ得る。別の実施形態では、凝縮プロセスが他の領域がマスクされたウエハの選択領域に行なわれる。例えば、それは、層３０５は、Ｎチャネル領域とＰチャネル領域とで異なる歪み特性を有することが望ましい場合がある。   In another embodiment, the template layer material may include other components such as silicon germanium carbon, silicon tin, and carbon in germanium carbon. The wafer 101 may include other transistors (not shown). In some embodiments, the layer 107 may be selectively formed in several wafer 101 regions. In another embodiment, layer 107 is formed on all wafers 101. Also, in some embodiments, the condensation process can be performed selectively on all layers 107. In another embodiment, the condensation process is performed on selected areas of the wafer with other areas masked. For example, it may be desirable for layer 305 to have different strain characteristics in the N-channel region and the P-channel region.

１実施形態では、半導体構造を形成する方法は、セミコンダクター・オン・インシュレータ（ＳＯＩ）構成を有するウエハを提供することを含む。ウエハは、絶縁体上に第１半導体層を備えている。第１半導体層は少なくとも２つの成分より形成されている。第１半導体層は、第１半導体層の第２部分に重なる第１部分を備えている。第１部分は少なくとも２つの成分のうちの第１濃度の第１成分を含み、第２部分は少なくとも２つの成分のうちの第２濃度の第１成分を含む。第１濃度は第２濃度よりも小さい。方法はさらに、第１半導体層上で凝縮プロセスを行い、第１半導体層の一部分を消費し、かつ第１半導体層の残りの部分の上に上記の少なくとも２つの成分のうちの第２成分を含む材料を形成することを含む。方法はさらに、材料を除去し、材料を除去した後に、残りの部分の上に第２成分を含む第２半導体層を形成することを含む。   In one embodiment, a method for forming a semiconductor structure includes providing a wafer having a semiconductor-on-insulator (SOI) configuration. The wafer includes a first semiconductor layer on an insulator. The first semiconductor layer is formed of at least two components. The first semiconductor layer includes a first portion that overlaps the second portion of the first semiconductor layer. The first portion includes a first component at a first concentration of at least two components, and the second portion includes a first component at a second concentration of at least two components. The first concentration is smaller than the second concentration. The method further includes performing a condensation process on the first semiconductor layer, consuming a portion of the first semiconductor layer, and applying a second component of the at least two components on the remaining portion of the first semiconductor layer. Forming a material comprising. The method further includes removing the material and, after removing the material, forming a second semiconductor layer including a second component over the remaining portion.

別の実施形態では、半導体構造を形成する方法は、ウエハを提供することを含む。ウエハは第１半導体層を備えている。第１半導体層はシリコンとゲルマニウムとを含む。第１半導体層は、第１濃度のゲルマニウムを有する第１部分と、第２濃度のゲルマニウムを有する第２部分とを備えている。第１部分は第２部分に重なっている。第１濃度は第２濃度よりも小さい。方法はさらに、第１半導体層上で凝縮プロセスを行い、第１半導体層の一部分を消費し、かつ第１半導体層の残りの部分に重なるシリコンを含む材料を形成することを含む。方法はさらに、シリコンを含む材料を除去し、シリコンを含む材料を除去した後に、残りの部分上にシリコンを含む第２半導体層を形成することを含む。   In another embodiment, a method for forming a semiconductor structure includes providing a wafer. The wafer includes a first semiconductor layer. The first semiconductor layer includes silicon and germanium. The first semiconductor layer includes a first portion having a first concentration of germanium and a second portion having a second concentration of germanium. The first part overlaps the second part. The first concentration is smaller than the second concentration. The method further includes performing a condensation process on the first semiconductor layer to form a material comprising silicon that consumes a portion of the first semiconductor layer and overlies the remaining portion of the first semiconductor layer. The method further includes removing the silicon-containing material, and after removing the silicon-containing material, forming a second semiconductor layer containing silicon on the remaining portion.

別の実施形態では、半導体装置を形成する方法は、セミコンダクター・オン・インシュレータ（ＳＯＩ）構成を有するウエハを提供することを含む。ウエハは、絶縁体上に第１半導体層を備えている。第１半導体層はゲルマニウムとシリコンとを含んでいる。第１半導体層は、第１半導体層の第２部分に重なる第１半導体層の第１部分を含んでいる。第１部分は、第１濃度のゲルマニウムを含み、第２部分は、第２濃度のゲルマニウムを含む。第１濃度は第２濃度よりも小さい。方法はさらに、第１半導体層上で酸化プロセスを行い、第１半導体層の一部分を消費し、かつ第１半導体層の残りの部分の上に酸化物を形成することを含む。方法はさらに、酸化物を除去し、酸化物を除去した後に、残りの部分をテンプレート層として用いて残りの部分の上にシリコンを含む第２半導体層を形成することを含む。方法はさらに、チャネル領域を含むトランジスタを形成することを含む。チャネル領域の少なくとも一部分は第２半導体層に位置する。   In another embodiment, a method of forming a semiconductor device includes providing a wafer having a semiconductor-on-insulator (SOI) configuration. The wafer includes a first semiconductor layer on an insulator. The first semiconductor layer contains germanium and silicon. The first semiconductor layer includes a first portion of the first semiconductor layer that overlaps a second portion of the first semiconductor layer. The first portion includes a first concentration of germanium and the second portion includes a second concentration of germanium. The first concentration is smaller than the second concentration. The method further includes performing an oxidation process on the first semiconductor layer, consuming a portion of the first semiconductor layer, and forming an oxide on the remaining portion of the first semiconductor layer. The method further includes removing the oxide and, after removing the oxide, forming a second semiconductor layer comprising silicon over the remaining portion using the remaining portion as a template layer. The method further includes forming a transistor including a channel region. At least a portion of the channel region is located in the second semiconductor layer.

本発明の特定の実施形態を図示し説明してきたが、当業者であれば、本明細書の教示に基づけば、本発明とその寄り広い態様から逸脱することなくさらなる変更および改変が行えることが理解される。したがって、特許請求の範囲は、そのような変更および改変を本発明の真の趣旨および範囲内にあるものとして自身の範囲内に包含するものとする。   While particular embodiments of the present invention have been illustrated and described, those skilled in the art will be able to make further changes and modifications without departing from the invention and its broader aspects, based on the teachings herein. Understood. Accordingly, the claims are intended to cover within their scope such changes and modifications as fall within the true spirit and scope of this invention.

本発明による半導体装置の製造中のある段階にあるウエハの１実施形態の部分断面図。1 is a partial cross-sectional view of an embodiment of a wafer at a stage during the manufacture of a semiconductor device according to the present invention. 本発明による半導体装置の製造中の別の段階にあるウエハの１実施形態の部分断面図。FIG. 6 is a partial cross-sectional view of one embodiment of a wafer at another stage during the manufacture of a semiconductor device according to the present invention. 本発明による半導体装置の製造中の別の段階にあるウエハの１実施形態の部分断面図。FIG. 6 is a partial cross-sectional view of one embodiment of a wafer at another stage during the manufacture of a semiconductor device according to the present invention. 本発明による半導体装置の製造中の別の段階にあるウエハの１実施形態の部分断面図。FIG. 6 is a partial cross-sectional view of one embodiment of a wafer at another stage during the manufacture of a semiconductor device according to the present invention.

Claims (28)

半導体構造を形成する方法であって、
セミコンダクター・オン・インシュレータ（ＳＯＩ）構成を有するウエハを提供することと、ウエハは、絶縁体上に第１半導体層を備え、第１半導体層は少なくとも２つの成分より形成され、第１半導体層は、第１半導体層の第２部分に重なる第１部分を備え、第１部分は前記少なくとも２つの成分のうちの第１濃度の第１成分を含み、第２部分は少なくとも２つの成分のうちの第２濃度の第１成分を含み、第１濃度は第２濃度よりも小さいことと、
第１半導体層上で凝縮プロセスを行い、第１半導体層の一部分を消費し、かつ第１半導体層の残りの部分の上に前記少なくとも２つの成分のうちの第２成分を含む材料を形成することと、
材料を除去することと、
材料を除去した後に、残りの部分の上に第２成分を含む第２半導体層を形成することと、
を含む方法。 A method of forming a semiconductor structure comprising:
Providing a wafer having a semiconductor-on-insulator (SOI) configuration, the wafer comprising a first semiconductor layer on an insulator, the first semiconductor layer being formed of at least two components, the first semiconductor layer comprising: A first portion overlying the second portion of the first semiconductor layer, the first portion including a first concentration of the first component of the at least two components, and the second portion of the at least two components. Including a first component of a second concentration, wherein the first concentration is less than the second concentration;
A condensation process is performed on the first semiconductor layer to form a material that consumes a portion of the first semiconductor layer and that includes a second component of the at least two components on the remaining portion of the first semiconductor layer. And
Removing material,
Forming a second semiconductor layer including a second component on the remaining portion after removing the material;
Including methods. 前記第２半導体層を形成することは、第１半導体層の残りの部分をテンプレート層として使用することを含む請求項１に記載の方法。   The method of claim 1, wherein forming the second semiconductor layer includes using the remaining portion of the first semiconductor layer as a template layer. 第１半導体層は、第１成分を含有するガスと第２成分を含有するガスとを第１の比でウエハ上にわたって流し、次に、第１成分を含有するガスと第２成分を含有するガスとを第２の比でウエハ上にわたって流すことにより形成され、前記第１の比は前記第２の比より大きい請求項１に記載の方法。   The first semiconductor layer causes the gas containing the first component and the gas containing the second component to flow over the wafer at a first ratio, and then contains the gas containing the first component and the second component. The method of claim 1, formed by flowing a gas over a wafer at a second ratio, wherein the first ratio is greater than the second ratio. 第１半導体層は化学蒸着（ＣＶＤ）層である請求項１に記載の方法。   The method of claim 1, wherein the first semiconductor layer is a chemical vapor deposition (CVD) layer. 前記第２半導体層はエピタキシ成長層である請求項１に記載の方法。   The method of claim 1, wherein the second semiconductor layer is an epitaxy growth layer. 第１成分はゲルマニウムであり、第２成分はシリコンである請求項１に記載の方法。   The method of claim 1, wherein the first component is germanium and the second component is silicon. ゲルマニウムは凝縮プロセス後に第１半導体層の残りの部分内で凝縮される請求項６に記載の方法。   The method of claim 6, wherein the germanium is condensed in the remaining portion of the first semiconductor layer after the condensation process. 第１半導体層の残りの部分は、凝縮プロセスの実行前の第１半導体層よりも弛緩したものであることを特徴とする請求項１に記載の方法。   The method of claim 1, wherein the remaining portion of the first semiconductor layer is more relaxed than the first semiconductor layer prior to performing the condensation process. 第１半導体層の第１部分および第２部分は、第１成分についての第１半導体層の戻り方向に勾配する部分の一部である請求項１に記載の方法。   The method of claim 1, wherein the first portion and the second portion of the first semiconductor layer are part of a portion that slopes in the return direction of the first semiconductor layer with respect to the first component. チャネル領域の少なくとも一部が第２半導体層に位置する、チャネル領域を含むトランジスタを形成することをさらに含む請求項１に記載の方法。   The method of claim 1, further comprising forming a transistor including the channel region, wherein at least a portion of the channel region is located in the second semiconductor layer. 残りの部分の濃度勾配は、第１成分の実質的に一様な分布を含む請求項１に記載の方法。   The method of claim 1, wherein the remaining concentration gradient comprises a substantially uniform distribution of the first component. 前記凝縮プロセスは、第１成分の酸化物よりも第２成分の酸化物を優先的に生成する請求項１に記載の方法。   The method of claim 1, wherein the condensation process preferentially produces a second component oxide over a first component oxide. 第１半導体層は、第１部分と第２部分との間に位置する第３部分を備え、第３部分は第３濃度の第１成分を含み、第３濃度は第２濃度よりも小さいが第１濃度よりも大きい請求項１に記載の方法。   The first semiconductor layer includes a third portion located between the first portion and the second portion, the third portion includes a first component having a third concentration, and the third concentration is smaller than the second concentration. The method of claim 1, wherein the method is greater than the first concentration. 半導体構造を形成する方法であって、
ウエハを提供することと、ウエハは第１半導体層を備え、第１半導体層はシリコンとゲルマニウムとを含み、第１半導体層は、第１濃度のゲルマニウムを有する第１部分と、第２濃度のゲルマニウムを有する第２部分とを備え、第１部分は第２部分に重なっており、第１濃度は第２濃度よりも小さいことと、
第１半導体層上で凝縮プロセスを行い、第１半導体層の一部分を消費し、かつ第１半導体層の残りの部分に重なるシリコンを含む材料を形成することと、
シリコンを含む材料を除去することと、
シリコンを含む材料を除去した後に、残りの部分上にシリコンを含む第２半導体層を形成することと、を含む方法。 A method of forming a semiconductor structure comprising:
Providing a wafer, the wafer comprising a first semiconductor layer, the first semiconductor layer comprising silicon and germanium, the first semiconductor layer comprising a first portion having a first concentration of germanium, and a second concentration; A second portion having germanium, wherein the first portion overlaps the second portion, the first concentration is less than the second concentration;
Performing a condensation process on the first semiconductor layer, consuming a portion of the first semiconductor layer and forming a material comprising silicon overlying the remaining portion of the first semiconductor layer;
Removing material containing silicon;
Forming a second semiconductor layer comprising silicon on the remaining portion after removing the material comprising silicon. 前記凝縮プロセスは酸化プロセスを含み、シリコンを含む材料は酸化シリコンを含んでいる請求項１４に記載の方法。   The method of claim 14, wherein the condensation process comprises an oxidation process and the silicon containing material comprises silicon oxide. 前記第２半導体層を形成することは、第１半導体層の残りの部分をテンプレート層として使用することを含む請求項１４に記載の方法。   The method of claim 14, wherein forming the second semiconductor layer includes using a remaining portion of the first semiconductor layer as a template layer. 第１半導体層は、シリコン含有ガスとゲルマニウム含有ガスとを第１の比でウエハ上にわたって流し、次に、シリコン含有ガスとゲルマニウム含有ガスとを第２の比でウエハ上にわたって流すことにより形成され、前記第２の比は前記第１の比より大きい請求項１４に記載の方法。   The first semiconductor layer is formed by flowing a silicon-containing gas and a germanium-containing gas over the wafer at a first ratio, and then flowing a silicon-containing gas and a germanium-containing gas over the wafer at a second ratio. The method of claim 14, wherein the second ratio is greater than the first ratio. 第１半導体層の残りの部分は、凝縮プロセスの実行前の第１半導体層よりも弛緩したものであることを特徴とする請求項１７に記載の方法。   The method of claim 17, wherein the remaining portion of the first semiconductor layer is more relaxed than the first semiconductor layer prior to performing the condensation process. 第１半導体層の第１部分および第２部分は、第１半導体層のゲルマニウムの戻り方向に勾配する部分の一部である請求項１４に記載の方法。   15. The method of claim 14, wherein the first and second portions of the first semiconductor layer are part of a portion of the first semiconductor layer that slopes in the germanium return direction. 残りの部分のゲルマニウム濃度勾配は、ゲルマニウムの実質的に一様な分布を含む請求項１４に記載の方法。   The method of claim 14, wherein the remaining portion of the germanium concentration gradient comprises a substantially uniform distribution of germanium. チャネル領域の少なくとも一部が第２半導体層に位置する、チャネル領域を含むトランジスタを形成することをさらに含む請求項１４に記載の方法。   The method of claim 14, further comprising forming a transistor including the channel region, wherein at least a portion of the channel region is located in the second semiconductor layer. 第２半導体層はストレインドシリコンであることを特徴とする請求項１４に記載の方法。   The method of claim 14, wherein the second semiconductor layer is strained silicon. 第１半導体層の第１部分は凝縮プロセスの実施の間に消費される請求項１４に記載の方法。   The method of claim 14, wherein the first portion of the first semiconductor layer is consumed during the performance of the condensation process. ウエハはセミコンダクター・オン・インシュレータ（ＳＯＩ）構成を有し、第１半導体層は絶縁体上に配置される請求項１４に記載の方法。   The method of claim 14, wherein the wafer has a semiconductor-on-insulator (SOI) configuration and the first semiconductor layer is disposed on an insulator. 第１半導体層の上で凝縮プロセスを行うことは、第１半導体層の選択領域上で凝縮プロセスを行なうことをさらに含む請求項１４に記載の方法。   The method of claim 14, wherein performing the condensation process on the first semiconductor layer further comprises performing a condensation process on selected regions of the first semiconductor layer. 半導体装置を形成する方法であって、
セミコンダクター・オン・インシュレータ（ＳＯＩ）構成を有するウエハを提供することと、ウエハは、絶縁体上に第１半導体層を備え、第１半導体層はゲルマニウムとシリコンとを含み、第１半導体層は、第１半導体層の第２部分に重なる第１半導体層の第１部分を含み、第１部分は第１濃度のゲルマニウムを含み、第２部分は第２濃度のゲルマニウムを含み、第１濃度は第２濃度よりも小さいことと、
第１半導体層上で酸化プロセスを行い、第１半導体層の一部分を消費し、かつ第１半導体層の残りの部分の上に酸化物を形成することと、
酸化物を除去することと、酸化物を除去した後に、残りの部分をテンプレート層として用いて残りの部分の上にシリコンを含む第２半導体層を形成することと、
チャネル領域の少なくとも一部分は第２半導体層に位置する、チャネル領域を含むトランジスタを形成することと、
を含む方法。 A method of forming a semiconductor device comprising:
Providing a wafer having a semiconductor-on-insulator (SOI) configuration, the wafer comprising a first semiconductor layer on an insulator, the first semiconductor layer comprising germanium and silicon, the first semiconductor layer comprising: The first portion of the first semiconductor layer overlies the second portion of the first semiconductor layer, the first portion includes a first concentration of germanium, the second portion includes a second concentration of germanium, and the first concentration is Less than 2 concentrations,
Performing an oxidation process on the first semiconductor layer, consuming a portion of the first semiconductor layer, and forming an oxide on the remaining portion of the first semiconductor layer;
Removing the oxide; after removing the oxide, forming a second semiconductor layer comprising silicon on the remaining portion using the remaining portion as a template layer;
Forming a transistor including the channel region, wherein at least a portion of the channel region is located in the second semiconductor layer;
Including methods. 残りの部分のゲルマニウム濃度勾配は、実質的に一様な分布を含む請求項２６に記載の方法。   27. The method of claim 26, wherein the remaining portion of the germanium concentration gradient comprises a substantially uniform distribution. 第１半導体層の残りの部分は、酸化プロセスの実行前の第１半導体層よりも弛緩したものであることを特徴とする請求項２６に記載の方法。   27. The method of claim 26, wherein the remaining portion of the first semiconductor layer is more relaxed than the first semiconductor layer prior to performing the oxidation process.
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009010883B4 (en) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Adjusting a non-silicon content in a semiconductor alloy during FET transistor fabrication by an intermediate oxidation process
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
CN102903636B (en) * 2011-07-25 2015-05-06 中芯国际集成电路制造(上海)有限公司 Manufacturing method of MOS (metal oxide semiconductor) transistor
CN102903635B (en) * 2011-07-25 2015-05-06 中芯国际集成电路制造(上海)有限公司 Manufacturing method of MOS (metal oxide semiconductor) transistor
US20140057399A1 (en) * 2012-08-24 2014-02-27 International Business Machines Corporation Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
CN105679645A (en) * 2014-11-17 2016-06-15 上海华力微电子有限公司 Improvement method for dislocation defect in embedded SiGe epitaxy

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031495A (en) * 2001-07-12 2003-01-31 Hitachi Ltd Manufacturing method of semiconductor device substrate and semiconductor device
JP2003197544A (en) * 2001-12-27 2003-07-11 Sumitomo Mitsubishi Silicon Corp Semiconductor substrate, field effect transistor, and their manufacturing methods
JP2005072054A (en) * 2003-08-27 2005-03-17 Toshiba Corp METHOD FOR MANUFACTURING STRAIN RELAXING SiGe SUBSTRATE

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3912559A (en) 1971-11-25 1975-10-14 Suwa Seikosha Kk Complementary MIS-type semiconductor devices and methods for manufacturing same
US4851257A (en) 1987-03-13 1989-07-25 Harris Corporation Process for the fabrication of a vertical contact
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5756898A (en) * 1994-06-27 1998-05-26 Texaco Inc. Passive acoustic method of measuring the effective internal diameter of a pipe containing flowing fluids
DE59707274D1 (en) 1996-09-27 2002-06-20 Infineon Technologies Ag Integrated CMOS circuit arrangement and method for its production
US5906951A (en) 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5846857A (en) 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US5943565A (en) 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US6124627A (en) 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6259138B1 (en) 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
US6369438B1 (en) * 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP3884203B2 (en) 1998-12-24 2007-02-21 株式会社東芝 Manufacturing method of semiconductor device
JP2001036054A (en) 1999-07-19 2001-02-09 Mitsubishi Electric Corp Manufacture of soi substrate
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
KR100392166B1 (en) * 2000-03-17 2003-07-22 가부시끼가이샤 도시바 Semiconductor device and method for manufacturing the same
US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020168802A1 (en) 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US6855436B2 (en) 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
US6475870B1 (en) 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture
WO2003025984A2 (en) 2001-09-21 2003-03-27 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
US6743651B2 (en) * 2002-04-23 2004-06-01 International Business Machines Corporation Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen
US6638802B1 (en) 2002-06-20 2003-10-28 Intel Corporation Forming strained source drain junction field effect transistors
JP3873012B2 (en) * 2002-07-29 2007-01-24 株式会社東芝 Manufacturing method of semiconductor device
US6955952B2 (en) 2003-03-07 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US7022593B2 (en) * 2003-03-12 2006-04-04 Asm America, Inc. SiGe rectification process
US7026249B2 (en) * 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
US7049660B2 (en) * 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031495A (en) * 2001-07-12 2003-01-31 Hitachi Ltd Manufacturing method of semiconductor device substrate and semiconductor device
JP2003197544A (en) * 2001-12-27 2003-07-11 Sumitomo Mitsubishi Silicon Corp Semiconductor substrate, field effect transistor, and their manufacturing methods
JP2005072054A (en) * 2003-08-27 2005-03-17 Toshiba Corp METHOD FOR MANUFACTURING STRAIN RELAXING SiGe SUBSTRATE

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