KR20070047307A - 그레이드된 반도체층 - Google Patents

그레이드된 반도체층 Download PDF

Info

Publication number
KR20070047307A
KR20070047307A KR1020077003816A KR20077003816A KR20070047307A KR 20070047307 A KR20070047307 A KR 20070047307A KR 1020077003816 A KR1020077003816 A KR 1020077003816A KR 20077003816 A KR20077003816 A KR 20077003816A KR 20070047307 A KR20070047307 A KR 20070047307A
Authority
KR
South Korea
Prior art keywords
semiconductor layer
layer
germanium
concentration
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020077003816A
Other languages
English (en)
Korean (ko)
Inventor
마리암 지. 사다카
숀 지. 토마스
테드 알. 화이트
천-리 리우
알렉산더 엘. 바
비치-엔 구엔
분-위 테안
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20070047307A publication Critical patent/KR20070047307A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
KR1020077003816A 2004-08-17 2005-08-08 그레이드된 반도체층 Withdrawn KR20070047307A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/919,952 2004-08-17
US10/919,952 US7241647B2 (en) 2004-08-17 2004-08-17 Graded semiconductor layer

Publications (1)

Publication Number Publication Date
KR20070047307A true KR20070047307A (ko) 2007-05-04

Family

ID=35910124

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077003816A Withdrawn KR20070047307A (ko) 2004-08-17 2005-08-08 그레이드된 반도체층

Country Status (6)

Country Link
US (1) US7241647B2 (enExample)
JP (1) JP2008510320A (enExample)
KR (1) KR20070047307A (enExample)
CN (1) CN100472761C (enExample)
TW (1) TWI371087B (enExample)
WO (1) WO2006023492A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009010883B4 (de) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
CN102903635B (zh) * 2011-07-25 2015-05-06 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制造方法
CN102903636B (zh) * 2011-07-25 2015-05-06 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制造方法
US20140057399A1 (en) * 2012-08-24 2014-02-27 International Business Machines Corporation Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer
CN105679645A (zh) * 2014-11-17 2016-06-15 上海华力微电子有限公司 嵌入式锗硅外延位错缺陷的改善方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3912559A (en) * 1971-11-25 1975-10-14 Suwa Seikosha Kk Complementary MIS-type semiconductor devices and methods for manufacturing same
US4851257A (en) * 1987-03-13 1989-07-25 Harris Corporation Process for the fabrication of a vertical contact
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5756898A (en) * 1994-06-27 1998-05-26 Texaco Inc. Passive acoustic method of measuring the effective internal diameter of a pipe containing flowing fluids
DE59707274D1 (de) * 1996-09-27 2002-06-20 Infineon Technologies Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5943565A (en) * 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US5846857A (en) * 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6124627A (en) * 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6259138B1 (en) * 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
JP3884203B2 (ja) 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
US6369438B1 (en) * 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2001036054A (ja) * 1999-07-19 2001-02-09 Mitsubishi Electric Corp Ｓｏｉ基板の製造方法
US6339232B1 (en) * 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
KR100392166B1 (ko) * 2000-03-17 2003-07-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법 및 반도체 장치
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020168802A1 (en) * 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
US6475870B1 (en) * 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture
JP3985519B2 (ja) * 2001-12-27 2007-10-03 株式会社Ｓｕｍｃｏ 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
EP1428262A2 (en) * 2001-09-21 2004-06-16 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
US6743651B2 (en) * 2002-04-23 2004-06-01 International Business Machines Corporation Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen
US6638802B1 (en) * 2002-06-20 2003-10-28 Intel Corporation Forming strained source drain junction field effect transistors
JP3873012B2 (ja) * 2002-07-29 2007-01-24 株式会社東芝 半導体装置の製造方法
US6955952B2 (en) * 2003-03-07 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US7022593B2 (en) * 2003-03-12 2006-04-04 Asm America, Inc. SiGe rectification process
US7026249B2 (en) * 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
US7049660B2 (en) * 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature
JP3967695B2 (ja) * 2003-08-27 2007-08-29 株式会社東芝 歪み緩和ＳｉＧｅ基板の製造方法

Also Published As

Publication number Publication date
WO2006023492A1 (en) 2006-03-02
CN101006580A (zh) 2007-07-25
JP2008510320A (ja) 2008-04-03
TWI371087B (en) 2012-08-21
CN100472761C (zh) 2009-03-25
US20060040433A1 (en) 2006-02-23
TW200620572A (en) 2006-06-16
US7241647B2 (en) 2007-07-10

Similar Documents

Publication Publication Date Title
US8110486B2 (en) Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer
KR101243997B1 (ko) 응력이 가해진 ｍｏｓ 디바이스 제조 방법
US7387925B2 (en) Integration of strained Ge into advanced CMOS technology
TWI484633B (zh) 用於多通道場效電晶體之中間產物及用於獲得中間產物的方法
US6723622B2 (en) Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
TWI387848B (zh) 主光罩層之形成
JP2694120B2 (ja) 疑似基板構造体
US7598145B2 (en) Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium
US20030107032A1 (en) Semiconductor device and production process thereof
JP5065676B2 (ja) 基板上に歪層を製造する方法及び層構造
US20090258478A1 (en) Method for providing a nanoscale, high electron mobility transistor (hemt) on insulator
KR101521555B1 (ko) 게르마늄 응축 공정을 이용한 기판 제조 방법 및 이를 이용한 반도체 소자의 제조 방법
US7238588B2 (en) Silicon buffered shallow trench isolation
JP5585268B2 (ja) 単結晶炭化珪素膜付き基材及び単結晶炭化珪素膜の製造方法並びに単結晶炭化珪素膜付き基材の製造方法
EP1790003A1 (en) Method of forming strained silicon materials with improved thermal conductivity
US20080153266A1 (en) Method to improve the selective epitaxial growth (seg) process
JP2010103142A (ja) 半導体装置の製造方法
KR20070047307A (ko) 그레이드된 반도체층
US6673696B1 (en) Post trench fill oxidation process for strained silicon processes
KR100742680B1 (ko) 실리콘-게르마늄층을 가진 반도체 웨이퍼 및 그 제조 방법
US7629211B2 (en) Field effect transistor and method of forming a field effect transistor
US20090302349A1 (en) Strained germanium field effect transistor and method of fabricating the same
CN100378906C (zh) 具有一平滑的磊晶层的半导体元件及其制造方法
EP1936670A2 (en) Method to improve the Selective Epitaxial Growth (SEG) Process
JPH09306844A (ja) 半導体装置の製造方法および半導体装置

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20070216

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid