JP5065676B2 - 基板上に歪層を製造する方法及び層構造 - Google Patents
基板上に歪層を製造する方法及び層構造 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
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Description
・歪を持たせる層に隣接する少なくとも一つの層を緩和させる工程
このために、層構造に対して、少なくとも一回の温度処理と酸化の両方又は一方を実施し、その結果欠陥領域を出発点として、転位を形成させて、その転位が、歪を持たせる層に隣接する層を緩和させるものである。
2 SOI基板、例えばSiO2 の絶縁体
3 SOI基板のSi表面層
4 層厚d4 の緩和させるエピタキシャル層(例えば、シリコン・ゲルマニウム)
4’ 緩和された領域
5 層厚d5 の歪を持たせる層
5’ 歪を持つ領域
6 層厚d6 の追加的な緩和させる層(例えば、シリコン・ゲルマニウム)
54 所定の(例えば、成長方向に対して低下する)Ge濃度分布を持つエピタキシャルSi−Ge層
66 マスク
99 欠陥領域
Claims (27)
- 基板(1,2)上に歪層を製造する方法であって、
基板(1)の上、或いは基板(1,2)上にエピタキシャル成長させた歪を持たせる層(3)の上に、緩和させる層(4)とその緩和させる層(4)の上の歪を持たせる層(5)を唯一回の成長プロセスでエピタキシャル成長させる工程と、
歪を持たせる層(5)の上に、歪を持たせる層(5)とは異なる歪度を有する少なくとも一つの緩和させる層(6)をエピタキシャル成長させる工程と、
イオン注入によって、基板(1)内に欠陥領域(99)を形成する工程と、
上記の工程により構成した層構造に対して、不活性雰囲気か、酸化性雰囲気か、窒化性雰囲気か、還元性雰囲気内で熱処理又は酸化を実施して、欠陥領域(99)から転位が拡がり、その転位によって、少なくとも一つの歪を持たせる層(5;3,5)に隣接する二つの層(4,6)の緩和を引き起こし、それによって、歪を持たせる層(5;3,5)を所望の歪を持った状態に移行させる工程と、
を有する方法。 - 当該の歪を持たせる層(5)の上にエピタキシャル成長させ、緩和させた少なくとも一つ層(6)を再び取り除くことを特徴とする請求項1に記載の方法。
- 当該の基板(1)の上、或いは基板(1,2)上にエピタキシャル成長させた歪を持たせる層(3)の上にエピタキシャル成長させた少なくとも一つの緩和させる層(4)の上に、少なくとも一つの歪層(5)を形成することを特徴とする請求項1又は2に記載の方法。
- 当該の歪を持たせる層(5)の上にエピタキシャル成長させ、緩和させた少なくとも一つ層(6)の除去を水素又はヘリウムの注入によって行うことを特徴とする請求項2に記載の方法。
- 当該の形成した欠陥領域(99)を切り離し面として使用することを特徴とする請求項1から4までのいずれか一つに記載の方法。
- 欠陥領域(99)を少なくとも一回のイオン注入によって形成することを特徴とする請求項1から5までのいずれか一つに記載の方法。
- 当該の少なくとも一回のイオン注入に関して、水素イオン、ヘリウムイオン又はSiイオンを選定することを特徴とする請求項6に記載の方法。
- 欠陥領域(99)を形成するために、3×1015〜4×1016cm−2の量の水素イオン又はヘリウムイオン、或いは1×1014cm−2の量のSiイオンを注入することを特徴とする請求項7に記載の方法。
- 欠陥領域(99)を形成するための注入に関して、水素イオンか、炭素イオンか、窒素イオンか、フッ素イオンか、ホウ素イオンか、シリコンイオンか、ゲルマニウムイオンか、硫黄イオンか、ネオンイオンか、アルゴンイオンか、クリプトンイオンか、層材料自体と同じ物質のイオンを用いることを特徴とする請求項1から8までのいずれか一つに記載の方法。
- 当該の層構造上に配置したマスク(66)を通してイオンを注入し、その層構造のイオンを注入された欠陥領域(99)だけが、緩和されるか、歪を持つか、緩和されるとともに歪を持つことを特徴とする請求項1から9までのいずれか一つに記載の方法。
- 水素とヘリウムの一方を50keVを上回るエネルギーで注入して、それに続く焼鈍の間に欠陥領域に集積させることによって、当該の切り離し面を形成することを特徴とする請求項5に記載の方法。
- 当該の切り離しのための水素イオンとヘリウムイオンの一方の注入量を低減することができることを特徴とする請求項11に記載の方法。
- 当該の層構造内における主要な結晶欠陥と基板内におけるエピタキシャル層構造の近くの広範な欠陥領域(99)の両方又は一方を形成することを特徴とする請求項1から12までのいずれか一つに記載の方法。
- 欠陥領域(99)を形成するための注入に関して、注入するイオンのエネルギーを、その平均到達範囲が、エピタキシャル層構造の全体的な層厚よりも大きくなるように選定することを特徴とする請求項1から13までのいずれか一つに記載の方法。
- 当該の熱処理を、550〜1200℃又は700〜950℃の温度範囲で実施することを特徴とする請求項1から14までのいずれか一つに記載の方法。
- 当該のエピタキシャル成長後における転位密度が、105cm−2より小さいことを特徴とする請求項1から15までのいずれか一つに記載の方法。
- 歪を持つ層(5’)と歪を持たない層(5)の両方又は一方を、1ナノメートルより小さい表面の粗さで形成することを特徴とする請求項10から16までのいずれか一つに記載の方法。
- 基板(1)上に、シリコンか、シリコン・ゲルマニウム(Si−Ge)か、シリコン・ゲルマニウム・カーボン(Si−GeC)か、シリコン・カーボン(SiC)を有する層構造を積み重ねることを特徴とする請求項1から17までのいずれか一つに記載の方法。
- 基板(1)上に、III−V族化合物半導体又はIII−V族窒化物か、II−VI族化合物半導体か、灰チタン石酸化物を有する層構造を積み重ねることを特徴とする請求項1から18までのいずれか一つに記載の方法。
- 少なくとも一つの緩和させる層(4,6)用の材料として、Si−Geを選定することを特徴とする請求項1から19までのいずれか一つに記載の方法。
- Si−Ge層(4,6)が、その層内のGe濃度が基板から徐々に又は段階的に減少する傾斜層であることを特徴とする請求項19又は20に記載の方法。
- 1〜2原子百分率の炭素追加含有量を持つ少なくとも一つの層を配置して、その層に緩和を引き起こすことを特徴とする請求項1から21までのいずれか一つに記載の方法。
- SOI(シリコン・オン・インシュレータ)基板(1,2,3)を選定することを特徴とする請求項1から22までのいずれか一つに記載の方法。
- 層厚が200ナノメートルを下回るエピタキシャル層構造を選定することを特徴とする請求項1から23までのいずれか一つに記載の方法。
- 基板(1)として、シリコンか、シリコン・ゲルマニウム(Si−Ge)か、シリコン炭化物(SiC)か、サファイヤか、III/V族化合物半導体を選定することを特徴とする請求項1から24までのいずれか一つに記載の方法。
- 当該の層構造から基板(1)と緩和させる層(4)を取り除いて、歪を持たせる層(5)と緩和させる層(6)をSiO2層を持つ基板上に接合することを特徴とする請求項1から25までのいずれか一つに記載の方法。
- イオン注入の間にマスクを使用することによって、マスクの下の領域(4’,5’)にp型MOSFETを製造し、マスクをしなかった領域(4,5)にn型MOSFETを製造することを特徴とする請求項1から26までのいずれか一つに記載の方法。
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DE10318284A DE10318284A1 (de) | 2003-04-22 | 2003-04-22 | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
PCT/DE2004/000780 WO2004095553A2 (de) | 2003-04-22 | 2004-04-15 | Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur |
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EP (1) | EP1616346A2 (ja) |
JP (1) | JP5065676B2 (ja) |
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DE102004048096A1 (de) * | 2004-09-30 | 2006-04-27 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
US7229901B2 (en) * | 2004-12-16 | 2007-06-12 | Wisconsin Alumni Research Foundation | Fabrication of strained heterojunction structures |
JP4654710B2 (ja) * | 2005-02-24 | 2011-03-23 | 信越半導体株式会社 | 半導体ウェーハの製造方法 |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FR2892855B1 (fr) * | 2005-10-28 | 2008-07-18 | Commissariat Energie Atomique | Procede de fabrication d'une structure en couches minces et structure en couches minces ainsi obtenue |
EP2469584A1 (en) * | 2005-12-09 | 2012-06-27 | Semequip, Inc. | Method of implanting ions |
FR2896255B1 (fr) * | 2006-01-17 | 2008-05-09 | Soitec Silicon On Insulator | Procede d'ajustement de la contrainte d'un substrat en un materiau semi-conducteur |
EP1808886A3 (fr) * | 2006-01-17 | 2009-08-12 | S.O.I.T.E.C. Silicon on Insulator Technologies | Procédé d'ajustement de la contrainte d'un substrat en un matériau semi-conducteur |
DE102006004870A1 (de) * | 2006-02-02 | 2007-08-16 | Siltronic Ag | Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur |
WO2007094057A1 (ja) * | 2006-02-15 | 2007-08-23 | Fujitsu Limited | 光デバイス |
DE102006010273B4 (de) * | 2006-03-02 | 2010-04-15 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung |
US7514726B2 (en) * | 2006-03-21 | 2009-04-07 | The United States Of America As Represented By The Aministrator Of The National Aeronautics And Space Administration | Graded index silicon geranium on lattice matched silicon geranium semiconductor alloy |
US7888197B2 (en) * | 2007-01-11 | 2011-02-15 | International Business Machines Corporation | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer |
US7494886B2 (en) | 2007-01-12 | 2009-02-24 | International Business Machines Corporation | Uniaxial strain relaxation of biaxial-strained thin films using ion implantation |
US8226767B2 (en) * | 2007-10-18 | 2012-07-24 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Hybrid bandgap engineering for super-hetero-epitaxial semiconductor materials, and products thereof |
US7943414B2 (en) * | 2008-08-01 | 2011-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
JP2011166129A (ja) * | 2010-01-15 | 2011-08-25 | Sumitomo Chemical Co Ltd | 半導体基板、電子デバイス及び半導体基板の製造方法 |
US8361889B2 (en) * | 2010-07-06 | 2013-01-29 | International Business Machines Corporation | Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator |
DE102010046215B4 (de) | 2010-09-21 | 2019-01-03 | Infineon Technologies Austria Ag | Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers. |
US8501600B2 (en) * | 2010-09-27 | 2013-08-06 | Applied Materials, Inc. | Methods for depositing germanium-containing layers |
US10361097B2 (en) * | 2012-12-31 | 2019-07-23 | Globalwafers Co., Ltd. | Apparatus for stressing semiconductor substrates |
US9614026B2 (en) | 2013-03-13 | 2017-04-04 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices |
FR3003686B1 (fr) | 2013-03-20 | 2016-11-04 | St Microelectronics Crolles 2 Sas | Procede de formation d'une couche de silicium contraint |
US9305781B1 (en) | 2015-04-30 | 2016-04-05 | International Business Machines Corporation | Structure and method to form localized strain relaxed SiGe buffer layer |
CN111733378B (zh) * | 2020-05-15 | 2022-12-13 | 中国兵器科学研究院宁波分院 | 一种钢表面的涂层结构及其制备方法 |
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DE19802977A1 (de) * | 1998-01-27 | 1999-07-29 | Forschungszentrum Juelich Gmbh | Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement |
US6326667B1 (en) * | 1999-09-09 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor devices and methods for producing semiconductor devices |
US6429061B1 (en) * | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
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US6562703B1 (en) * | 2002-03-13 | 2003-05-13 | Sharp Laboratories Of America, Inc. | Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content |
DE10218381A1 (de) * | 2002-04-24 | 2004-02-26 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer oder mehrerer einkristalliner Schichten mit jeweils unterschiedlicher Gitterstruktur in einer Ebene einer Schichtenfolge |
US6972245B2 (en) | 2002-05-15 | 2005-12-06 | The Regents Of The University Of California | Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures |
US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
DE10310740A1 (de) | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen |
JP2004281764A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置およびその製造方法 |
DE10318283A1 (de) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
US7049660B2 (en) * | 2003-05-30 | 2006-05-23 | International Business Machines Corporation | High-quality SGOI by oxidation near the alloy melting temperature |
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WO2004095553A3 (de) | 2004-12-23 |
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WO2004095553A2 (de) | 2004-11-04 |
EP1616346A2 (de) | 2006-01-18 |
US7416965B2 (en) | 2008-08-26 |
DE10318284A1 (de) | 2004-11-25 |
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