EP1616346A2 - Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur - Google Patents

Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Info

Publication number
EP1616346A2
EP1616346A2 EP04727506A EP04727506A EP1616346A2 EP 1616346 A2 EP1616346 A2 EP 1616346A2 EP 04727506 A EP04727506 A EP 04727506A EP 04727506 A EP04727506 A EP 04727506A EP 1616346 A2 EP1616346 A2 EP 1616346A2
Authority
EP
European Patent Office
Prior art keywords
layer
strained
substrate
layer structure
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04727506A
Other languages
German (de)
English (en)
French (fr)
Inventor
Siegfried Mantl
Bernhard HOLLÄNDER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Forschungszentrum Juelich GmbH
Original Assignee
Forschungszentrum Juelich GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forschungszentrum Juelich GmbH filed Critical Forschungszentrum Juelich GmbH
Publication of EP1616346A2 publication Critical patent/EP1616346A2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
EP04727506A 2003-04-22 2004-04-15 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur Withdrawn EP1616346A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10318284A DE10318284A1 (de) 2003-04-22 2003-04-22 Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
PCT/DE2004/000780 WO2004095553A2 (de) 2003-04-22 2004-04-15 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Publications (1)

Publication Number Publication Date
EP1616346A2 true EP1616346A2 (de) 2006-01-18

Family

ID=33304880

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04727506A Withdrawn EP1616346A2 (de) 2003-04-22 2004-04-15 Verfahren zur herstellung einer verspannten schicht auf einem substrat und schichtstruktur

Country Status (5)

Country Link
US (1) US7416965B2 (ja)
EP (1) EP1616346A2 (ja)
JP (1) JP5065676B2 (ja)
DE (1) DE10318284A1 (ja)
WO (1) WO2004095553A2 (ja)

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DE102004048096A1 (de) * 2004-09-30 2006-04-27 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7229901B2 (en) * 2004-12-16 2007-06-12 Wisconsin Alumni Research Foundation Fabrication of strained heterojunction structures
JP4654710B2 (ja) * 2005-02-24 2011-03-23 信越半導体株式会社 半導体ウェーハの製造方法
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2892855B1 (fr) * 2005-10-28 2008-07-18 Commissariat Energie Atomique Procede de fabrication d'une structure en couches minces et structure en couches minces ainsi obtenue
EP1958245B1 (en) * 2005-12-09 2013-10-16 Semequip, Inc. Method for the manufacture of semiconductor devices by the implantation of carbon clusters
FR2896255B1 (fr) * 2006-01-17 2008-05-09 Soitec Silicon On Insulator Procede d'ajustement de la contrainte d'un substrat en un materiau semi-conducteur
EP1808886A3 (fr) * 2006-01-17 2009-08-12 S.O.I.T.E.C. Silicon on Insulator Technologies Procédé d'ajustement de la contrainte d'un substrat en un matériau semi-conducteur
DE102006004870A1 (de) * 2006-02-02 2007-08-16 Siltronic Ag Halbleiterschichtstruktur und Verfahren zur Herstellung einer Halbleiterschichtstruktur
WO2007094057A1 (ja) * 2006-02-15 2007-08-23 Fujitsu Limited 光デバイス
DE102006010273B4 (de) * 2006-03-02 2010-04-15 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem spannungskompensierten Schichtstapel mit geringer Defektdichte, Schichtstapel und dessen Verwendung
US7514726B2 (en) * 2006-03-21 2009-04-07 The United States Of America As Represented By The Aministrator Of The National Aeronautics And Space Administration Graded index silicon geranium on lattice matched silicon geranium semiconductor alloy
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US7494886B2 (en) 2007-01-12 2009-02-24 International Business Machines Corporation Uniaxial strain relaxation of biaxial-strained thin films using ion implantation
US7769135B2 (en) * 2007-10-18 2010-08-03 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration X-ray diffraction wafer mapping method for rhombohedral super-hetero-epitaxy
JP5552276B2 (ja) * 2008-08-01 2014-07-16 株式会社半導体エネルギー研究所 Soi基板の作製方法
JP2011166129A (ja) * 2010-01-15 2011-08-25 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス及び半導体基板の製造方法
US8361889B2 (en) * 2010-07-06 2013-01-29 International Business Machines Corporation Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
DE102010046215B4 (de) * 2010-09-21 2019-01-03 Infineon Technologies Austria Ag Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers.
US8501600B2 (en) * 2010-09-27 2013-08-06 Applied Materials, Inc. Methods for depositing germanium-containing layers
US10361097B2 (en) 2012-12-31 2019-07-23 Globalwafers Co., Ltd. Apparatus for stressing semiconductor substrates
US9614026B2 (en) 2013-03-13 2017-04-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices
FR3003686B1 (fr) 2013-03-20 2016-11-04 St Microelectronics Crolles 2 Sas Procede de formation d'une couche de silicium contraint
US9305781B1 (en) 2015-04-30 2016-04-05 International Business Machines Corporation Structure and method to form localized strain relaxed SiGe buffer layer
CN111733378B (zh) * 2020-05-15 2022-12-13 中国兵器科学研究院宁波分院 一种钢表面的涂层结构及其制备方法

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US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
DE19802977A1 (de) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
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JP3875040B2 (ja) * 2001-05-17 2007-01-31 シャープ株式会社 半導体基板及びその製造方法ならびに半導体装置及びその製造方法
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
JP4854871B2 (ja) * 2001-06-20 2012-01-18 株式会社Sumco 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
JP2003008022A (ja) * 2001-06-20 2003-01-10 Mitsubishi Materials Silicon Corp 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
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WO2003098664A2 (en) 2002-05-15 2003-11-27 The Regents Of The University Of California Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures
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JP2004281764A (ja) * 2003-03-17 2004-10-07 Seiko Epson Corp 半導体装置およびその製造方法
DE10318283A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
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Also Published As

Publication number Publication date
JP2006524427A (ja) 2006-10-26
DE10318284A1 (de) 2004-11-25
WO2004095553A3 (de) 2004-12-23
US20060211221A1 (en) 2006-09-21
JP5065676B2 (ja) 2012-11-07
US7416965B2 (en) 2008-08-26
WO2004095553A2 (de) 2004-11-04

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