TWI387848B - 主光罩層之形成 - Google Patents
主光罩層之形成 Download PDFInfo
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- TWI387848B TWI387848B TW093128720A TW93128720A TWI387848B TW I387848 B TWI387848 B TW I387848B TW 093128720 A TW093128720 A TW 093128720A TW 93128720 A TW93128720 A TW 93128720A TW I387848 B TWI387848 B TW I387848B
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- 230000015572 biosynthetic process Effects 0.000 title description 5
- 238000000034 method Methods 0.000 claims description 134
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 70
- 229910052732 germanium Inorganic materials 0.000 claims description 54
- 239000004065 semiconductor Substances 0.000 claims description 50
- 238000007254 oxidation reaction Methods 0.000 claims description 43
- 230000003647 oxidation Effects 0.000 claims description 42
- 239000000460 chlorine Substances 0.000 claims description 26
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 24
- 229910052801 chlorine Inorganic materials 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 24
- 238000005345 coagulation Methods 0.000 claims description 19
- 230000015271 coagulation Effects 0.000 claims description 18
- 238000009833 condensation Methods 0.000 claims description 11
- 230000005494 condensation Effects 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 4
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 64
- 239000000463 material Substances 0.000 description 32
- 239000007789 gas Substances 0.000 description 29
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 24
- 229910052707 ruthenium Inorganic materials 0.000 description 23
- 150000002500 ions Chemical class 0.000 description 20
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 17
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 17
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 15
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 13
- 239000001301 oxygen Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 229910052760 oxygen Inorganic materials 0.000 description 12
- 238000005121 nitriding Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- 229910052715 tantalum Inorganic materials 0.000 description 10
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 8
- 229910021529 ammonia Inorganic materials 0.000 description 7
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical group [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- 229910052691 Erbium Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- KCFIHQSTJSCCBR-UHFFFAOYSA-N [C].[Ge] Chemical compound [C].[Ge] KCFIHQSTJSCCBR-UHFFFAOYSA-N 0.000 description 3
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical group [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000003085 diluting agent Substances 0.000 description 3
- -1 erbium ions Chemical class 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- GVFOJDIFWSDNOY-UHFFFAOYSA-N antimony tin Chemical compound [Sn].[Sb] GVFOJDIFWSDNOY-UHFFFAOYSA-N 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- IAOQICOCWPKKMH-UHFFFAOYSA-N dithieno[3,2-a:3',2'-d]thiophene Chemical compound C1=CSC2=C1C(C=CS1)=C1S2 IAOQICOCWPKKMH-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- DDJAGKOCVFYQOV-UHFFFAOYSA-N tellanylideneantimony Chemical compound [Te]=[Sb] DDJAGKOCVFYQOV-UHFFFAOYSA-N 0.000 description 1
- 150000004772 tellurides Chemical class 0.000 description 1
- 150000003609 titanium compounds Chemical class 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本申請案於2004年8月17日在美國提出專利申請,其係於2003年9月25日提出申請之專利申請案第10/670,928號之部份接續申請案。
概言之,本發明係關於半導體電路,且具體而言,係關於一應變型半導體層之形成。
對於某些應用而言,人們期望在一絕緣體上製作一應變矽層,例如,一絕緣體上矽(SOI)構造。一應變矽層係一由晶格間距不同於天然矽(例如,一鬆弛矽晶體)之晶格間距(例如,5.43095埃)之矽構成之層。對於1%之拉伸應力,應變矽間距之一實例係5.4843埃。一應變係層可提供較一鬆弛矽晶體層更大之電子和空穴遷移率。
形成一應變矽層之一方法係在一晶格間距較天然矽晶體之晶格間距為大之主光罩層上形成一矽層。在該主光罩層頂部形成(例如,藉由磊晶沈積)之所獲得矽在承受應力後可提供一更大或更小之晶格間距。
圖1顯示一SOI基板構造之實例中之一先前技術晶圓101,該晶圓包括一位於一絕緣層105(例如,二氧化矽)上之矽鍺(SiGe)層103。絕緣層105係位於一層107上。
參照圖2,為增加一主光罩層中鍺的含量並藉此增加其晶格間距,層103經受一氧化製程以使層103之底部部分205
中之鍺量富集。其頂部部分係經氧化後形成SiO2
層203。在氧化製程期間,來自層103頂部部分之鍺原子注入部分205並擴散至整個205。在一實例中,該氧化製程包括在含氧氣且一惰性氣體(例如,氬或N2
)作為稀釋劑之氣氛下將晶圓101加熱至1200℃。
然後,去除(例如,藉由蝕刻)所獲得之SiO2
層203。然後,在層205上生長(例如,磊晶)一矽層。由於層205具有一較大的晶格間距,該頂部矽層可在雙軸拉應力下提供一較天然存在之矽晶體為大之晶格間距。
此製程之一問題係主光罩層205不能完全鬆弛,此乃因該晶格間距與一具有層205之鍺百分數之晶體不能完全對應。因此,並非所有注入鍺原子均位於晶格點上,該層承受下面絕緣層105之應力,且層205之隙間鍺及矽原子傾向於形成缺陷。
此一製程可能出現之另一問題係鍺可能不會充分擴散至該矽鍺層之其餘部分中。因此,與該其餘層之下部具有高鍺濃度相反,該其餘層之頂部部分可具有相對高之鍺濃度。該主光罩層中鍺濃度之該等差異可導致差排,此差排可導致在該差排區域形成一功能障礙半導體元件。
圖3顯示一矽鍺晶體之晶格301之二維視圖,該晶格具有較一具有相同鍺含量之鬆弛矽鍺晶體為小之晶格間距。圖3顯示隙間鍺原子(例如,305)及隙間矽原子(例如,311)位於晶格點(例如,313與315)之間。該等隙間原子可導致缺陷在該矽鍺主光罩層中及隨後所形成應變矽層中擴展。
業內需要一用於形成一主光罩層之改良方法。
本發明提供一種用於形成應變半導體層之製程。該製程包括使一含氯氣體(例如,氯化氫、氯氣、四氯化碳及三氯乙烷)流過晶圓,且同時加熱該晶圓。在一實例中,該含氯氣體係在一凝結製程期間在一作為一主光罩層之半導體層上流過,以形成一應變半導體層(例如,應變矽)。在其他實例中,該含氯氣體係在凝結製程後該晶圓之後烘焙期間流過。
下文詳細闡述本發明之實施方式。此說明意欲舉例闡述本發明且不應理解為具有限制性。
頃發現,提供一製程用於在形成於一絕緣層上之主光罩層材料層中注入空穴可使鍺(或其他晶體晶格間距修飾晶種)原子佔據一主光罩層之晶格點,藉此增加該主光罩層晶體晶格之有效晶格間距。
圖4係一晶圓經受一本發明之滲氮製程後之局部側視圖。晶圓401包括一由(例如)位於層407上之二氧化矽構成之絕緣層405。層407係由矽鍺構成,但亦可由其他材料構成,例如,複晶矽、單晶矽、非晶形矽、玻璃或石英。絕緣層405可藉由以下方式製備:形成一矽鍺層並隨之將氧植入該矽鍺層,隨後退火以形成絕緣層405。圖4所示之結構亦可藉由以下方式形成:將一包含SiGe之第二晶圓黏結至層405上並隨後切割該第二晶圓之一部分,在絕緣層405上留下一
矽鍺層。此一矽鍺層可具有較圖4所示之層403為厚之厚度。在其他實施例中,絕緣層405可延伸至該晶圓之底部。在再其他實施例中,一包含矽之晶圓可黏結至絕緣層405並隨後切割,在層405上留下一矽層。一SiGe層可用一磊晶製程形成於一矽層上。
層409係一藉由使層405上之矽鍺層(未圖示)經受一滲氮製程而生長之氮化矽層。在一實施例中,該滲氮製程包括在一高溫下使氨(NH3
)流過絕緣層405上之矽鍺層。氨中之氮與該矽鍺層之矽反應,生長形成氮化矽層409,藉此將該矽鍺層降低至圖4中所示矽鍺層403之厚度。在該滲氮製程期間,將空穴注入該矽鍺層之其餘部分(層403)並擴散至整個層403。一空穴係一晶格點中缺失原子之空間。同樣在該滲氮製程期間,將來自該矽鍺層頂部部分之鍺原子注入該矽鍺層之其餘部分(層403)。該等鍺原子與層403之該等空穴再結合,變得可替代。隙間鍺(及矽)原子亦與該等空穴再結合,變得可替代。
空穴係藉由層403之晶格中之矽原子向上擴展與該氨之氮結合形成一氮化矽層409而注入層403。由於鍺不與氨反應,故鍺原子係藉由擴散注入其餘矽鍺層403之晶格中。
圖5顯示一矽鍺晶格501之實例。晶格501包括空穴503及505。在該滲氮製程期間,鍺原子(例如,隙間鍺原子507)與空穴(例如,503)再結合以填充該晶格結構。
請重新參照圖4,藉由選擇性蝕刻矽鍺層403來剝除氮化物層409。層403係作為一主光罩層,用於隨後塗覆應變磊
晶矽層(參見圖10之層1009)。
將空穴注入一主光罩層,可使現有隙間原子在該主光罩層之晶體晶格中具可替代性。此可降低該主光罩層中隙間原子之數量且藉此降低該主光罩層之缺陷密度。而且,將空穴注入一主光罩層可允許重建絕緣層405與主光罩層403間之界面,藉此容許主光罩層403具有一更高之鬆弛度。
在其他實施例中,可使用其他製程將空穴注入主光罩層材料中。舉例而言,位於層405上之矽鍺主光罩層材料層可經受一矽化物製程,使金屬(例如,鈦)沈積於該主光罩層材料上並與該主光罩層材料之矽反應(加熱時),形成一矽鈦化合物層(大約在圖4所示層409之位置)。在此矽化物製程期間,空穴係藉由其餘部分之矽原子向上擴展與該鈦結合形成矽化鈦層(例如,在409之位置)而注入該矽鍺主光罩材料之其餘部分(例如,層403)中。
在另一實施例中,一主光罩層材料可經受一氧氮化物製程,以將鍺富集於該主光罩層中並將空穴注入該主光罩層。在一氧氮化物製程之一實例中,氨及氧流過該主光罩層材料之表面以自該主光罩層材料層上生長一氧氮化物層。在該氧氮化製程期間,藉由彼部分中之矽原子向上擴展與該氨之氮及氧結合,在對應於圖4所示層409之位置形成一氧氮化矽層,而使空穴被注入該主光罩材料層之下部部分。由於鍺不與氨及氧反應,故該等鍺原子係藉由擴散而注入該主光罩層材料下部部分(位於圖4所示層403之位置)之矽鍺晶格中。然後,去除該氧氮化物層,其中該主光
罩材料之下部部分(例如,403)係用作該主光罩。在其他實施例中,可使一氧化氮氣體(NO)或氧化亞氮氣體(N2
O)流過該主光罩層材料之表面,以自該主光罩層材料層上生長一氧氮化物層。
在再一實施例中,一主光罩材料層可經受一氧化製程,其中隨氧氣引入一含氯氣體(例如,氯化氫氣體(HCl)、氯氣(Cl2
)、四氯化碳氣體(CCl4
)或三氯乙烷氣體(C2
H3
Cl3
)),以將鍺原子及空穴注入該主光罩層中。在此一氧化製程之一實施例中,使HCl與氧氣(且在某些實施例中,氬或氮氣(N2
)作為稀釋劑)在1100℃下流過該主光罩材料層,以在該主光罩材料層上生長一氧化矽層。在一實施例中,該HCl之濃度係6%,但在其他實施例中亦可為其他濃度,例如,在其他實施例中為0.1至10%。端視該氧化設備而定,在其他實施例中該HCl濃度可更高。該氧化矽層係位於圖4所示層409之對應位置。據信,氯化物之引入可增加該氧化製程之氧化速度並將空穴注入該主光罩材料層。
使用HCl(或其他含氯氣體)之氧化製程可存在之一其他優點係該氧化製程可在一甚低於常用氧化製程之溫度(例如,在某些實施例中,在1050至1100℃)下實施。由於在一氧化製程期間,該主光罩材料層之其餘部分富集鍺,故該富鍺層之熔點降低。因此,在一較低溫度(1050至1100℃,而非1200℃)下實施氧化之能力可允許實施氧化製程並避免該主光罩材料層融化。而且,在較低溫度下實施氧化之能力可使該氧化製程易於與CMOS製程向整合。
而且,在一氧化製程中引入HCl(或其他含氯氣體)可增加氧化速度,藉此減少實施氧化所需之時間。而且,在某些實施例中,該HCl並不影響所生長氧化物之品質。因此,該氧化物在該氧化物層與該主光罩材料之其餘層之間保持一高選擇性。
在其他實施例中,該含氯氣體之氧化係在介於700至1200℃間之溫度下實施,但在其他實施例中亦可在其他溫度下實施。在其他實施例中,可以在該氧化製程之至少一部分期間引入HCl或其他含氯氣體之方式實施該氧化。舉例而言,在一實施例中,該氧化係在1050℃下使用氧氣實施30分鐘,並隨後在1050℃下使用氧及HCl氣體實施30分鐘。在其他實施例中,在該氧化製程期間可多次引入該HCl。在其他實施例中,該氧化及蝕刻循環可分多個步驟實施,以使該空穴注入製程更有效並簡化該氧化物蝕刻製程。
在其他實施例中,其他材料可用作主光罩層材料,例如,矽鍺碳(Si1-x-y
Gex
Cy
,其中Ge含量>C含量且x>y)、矽錫(SiSn)、矽碳(Si1-y
,Cy
)、矽錫鍺(SiSnGe)及鍺碳(GeC)。
在某些實施例中,在去除氮化矽層409(在某些實施例中,一氧氮化矽、矽化鈦、氧化矽層)後,可對晶圓實施一後凝結步驟。在該氧化製程期間,層403之矽向上擴展與氧結合以生長一氧化矽層604(參見圖6),並藉此消耗層403之一部分。由於鍺不與氧反應,故該等鍺原子係藉由擴散注入層403(圖6中之層603)其餘部分之晶格中。然後蝕刻層604,其中層603係用作一主光罩層。由於該後氧化製程,
層603之應變較層403為大。在其他實施例中,矽化物或氧氮化物製程後可實施一後氧化製程。
在其他實施例中,空穴注入製程之實施可在凝結製程之後(例如,氧化該主光罩層材料之後)實施。
圖7係一晶圓之局部剖視圖,其中該晶圓首先經受一氧化製程並隨後經受一滲氮製程,以將空穴注入該主光罩層。層706與709係藉由對一應變矽鍺層(例如,類似於圖2之層205)實施一滲氮製程而形成。該應變矽鍺層藉由一氧化製程形成,在該氧化製程中一氧化物層(例如,203)生長於一矽鍺層(例如,圖1之103)上。由於鍺原子自該鍺層之經消耗部分擴散至所獲得層,故所獲得應變矽鍺層(例如,層205)為鍺豐富。由於該氧化製程並非一空穴產生製程,一部分經擴散鍺原子在該應變矽鍺層(例如,205)之晶格中成為隙間原子。之後,去除該氧化物層(例如,205)。在其他實施例中,僅去除該氧化物層(例如,205)之一部分。
在一後續滲氮製程中,一氮化矽層709自該應變矽鍺層(例如,205)生長出來。空穴係藉由層706晶格中之矽原子向上擴展與氮結合形成氮化矽層709而注入其餘矽鍺層706中。該等空穴與該富鍺應變矽鍺層706之隙間鍺再結合以減少隙間鍺之數量。而且,該應變矽鍺(例如,205)經消耗部分之鍺原子藉由擴散注入層706之晶格中。去除層709,然後層706用作一主光罩層。由於空穴之注入,所獲得層706之應變較前述應變矽鍺層(例如,205)為小。
圖8及9顯示一處於另一空穴注入製程之各階段期間之晶
圓。在圖8中,氮(809)係植入位於絕緣層805上之主光罩材料層803(例如,SiGe)之頂部部分811中。在某些實施例中,該氮係以大於1013
個原子/平方公分之劑量且以介於10至50 keV間之能量植入。然後,使晶圓801經受一生長一氧氮化物層905的氧化製程,且將空穴及鍺原子注入層803之底部部分907之晶格中(參見圖9)。之後,蝕刻層905,其中部分907係用作該主光罩層。
在其他實施例中,一主光罩材料層可經受一氧化製程並然後經受一後續惰性氣體後烘焙(退火)製程。在一實施例中,一氫氣後烘焙製程係在T=900至1100℃下實施1至100分鐘,其間H2
氣體以PH2
=1-100托之壓力流過該SiO2
層。在該惰性氣體後烘焙製程期間,將空穴注入主光罩材料之其餘層。在其他實施例中,在低氧壓力(PO2
)下可使用諸如氬等其他惰性氣體。
在其他實施例中,可使用含氯氣體實施該後烘焙製程。在一實施例中,在一凝結製程(例如,氧化,滲氮)後,在1050℃下加熱一晶圓30分鐘,其間HCl(例如,6%之濃度)以(例如)PH2
=1-100托之壓力下流過該晶圓。在其他實施例中,在該後烘焙製程期間,其他氣體(例如,惰性氣體,例如,氬、N2
及氦)亦可與HCl一起流過。在其他實施例中,在該後烘焙製程期間,該晶圓可在其他溫度(例如,700至1200℃或其他溫度)下加熱,該後烘焙可在其他氣體之存在下實施,該後烘焙可以其他氣體濃度(例如,0.1至10%之HCl濃度)實施,該後烘焙可在其他氣體壓力(1至100托)下及/或以
其他持續時間(例如,在某些實施例中,1至1200分鐘)實施。
使用含氯氣體實施一後烘焙可將空穴注入該矽鍺層之其餘部分。此亦可因應變誘導擴散之增強而改進擴散,此可導致一更均勻之鍺分佈(減少鍺堆積)及一更鬆弛之矽鍺層。
參照圖10,在絕緣層1005上形成一主光罩層1003(例如,藉由一類似於上述任一製程之製程)後,在主光罩層1003上形成(例如,磊晶生長)一應變矽層1009。之後,在應變矽及主光罩層中形成諸如電晶體等元件。在一實施例中,該電晶體之通道區域係形成於應變矽層1009中。
在其他實施例中,一單晶矽層係形成於該絕緣層(例如,405)上。然後,一矽鍺(或其他主光罩材料)層可形成於該矽材料層上。在空穴注入製程及氧化製程期間(在某些實施例中),可將鍺原子及空穴注入該矽層,其中該矽層可作為該主光罩層之一部分。
圖11至16顯示半導體元件製造之各階段中晶圓101之剖面視圖。圖11至16之視圖所闡明之方法包括另一空穴注入製程。
參照圖11,晶圓1101具有一SOI構造,其中一絕緣體1105位於矽基板1103上。一矽層1106位於絕緣體1105上。一矽鍺層1107位於層1105上。
在所示實施例中,P-通道區域1113係由光阻1109遮罩。然後,在矽鍺層1107內選擇性植入離子1111以在N-通道區域1115內形成植入區1203(參見圖12)。該等植入可注入空穴並在區域1203中形成其他類型之點缺陷。在其他實施例
中,P-通道區域1113係由一介電或硬材料(例如,頂部有光阻之氮化物或氧化物)遮罩。
在一實施例中,可在遮罩區域1113之前於層1107上形成一矽覆蓋層(200埃)(未圖示)。
在一實施例中,係以較層1107之總厚度為小之深度植入該等離子。在層1107為1000埃之一實施例中,離子1111係植入一介於100至900埃間之深度。在其他實施例中,離子1111係植入矽層1106之上約100埃。在一實施例中,離子1111係植入層1106。
在一實施例中,離子1111包括鍺。在其他實施例中,離子1111包括矽、硼、砷、磷或其組合。在某些實施例中,不同類型之離子植入不同深度。在某些實施例中。不同類型及深度之離子係在不同之時間植入。在一實施例中,矽離子可植入矽鍺層1107中且鍺離子可植入矽層1106中。
在該等植入離子包括硼、磷或砷之某些實施例中,除注入空穴外,該等離子亦可用於將井摻雜至一期望導電性。在一實施例中,離子1111包括硼,以給N-通道區域1115提供一經摻雜之井區域,用於隨後在彼區域形成之電晶體。在一實施例中,離子1111包括以5e12原子/平方公分之劑量及10 KeV之能量植入之硼。
在其他實施例中,離子1111包括以3e15原子/平方公分之劑量及3 KeV之能量植入之硼。在其他實施例中,離子1111包括以1e13原子/平方公分之劑量及40 KeV之能量植入之鍺。在另一實施例中,離子1111可以其他劑量及/或以其他
能量植入。
圖12顯示光阻1109去除後之晶圓1101。在其他實施例中,隨後可遮罩區域1115,其中可在用於在層1107中注入空穴的區域1113中植入離子。在此一實施例中,N-通道區域與P-通道區域之空穴注入量可不同。此一差異可用於以差別方式控制隨後在P-通道區域與N-通道區域中所形成之矽層(例如,1503)之應變。
圖13顯示在晶圓1101上實施一凝結作業後之晶圓1101。在一實施例中,該凝結作業包括一氧化製程,該製程消耗層1107之一部分並在矽鍺層1107之其餘部分上形成氧化物層1305。在所示之實施例中,該氧化製程後的矽鍺層1107之其餘部分係由層1307表示。在該氧化製程期間,層1107之消耗部分中之鍺原子擴散至層1107之其餘部分,以增加其餘部分中之鍺濃度。層1107之鍺原子亦可擴散至層1106。圖13中之層1307表示該氧化製程後的層1106及層1107之其餘部分。
在層1107中植入離子1111可在彼層中注入空穴,此使得鍺在凝結製程期間更快且更均勻地擴散於該層之其餘部分中。因此,與無先前植入之氧化製程(或其他凝結製程)相比,鍺堆積可減少。
在一實施例中,該凝結製程包括在(例如)1050度之溫度下使氧氣及HCl氣體(例如,6%)或其他含氯氣體(且在某些實施例中氬或氮(N2
)作為稀釋劑)流過晶圓1101(例如)30至60分鐘。在其他實施例中,可使用其他氧化製程。在其他
實施例中。可利用其他凝結製程(例如,滲氮、氧氮化物)。
在所示實施例中,在區域1115中之層1107中植入離子1111(例如,鍺離子)可導致無預凝結植入區域之氧化速率增加。因此,在區域1115中,氧化矽層1305較厚,且在一既定氧化時間下,由於其氧化速率較區域1113增加,所消耗之層1107較多。因此,層1307在區域1113中較在區域1115中為厚。
圖14顯示氧化物1305去除後之晶圓1101。在某些實施例中,該晶圓之後烘焙(例如,用HCl氣體)可在凝結製程後實施。
圖15顯示一應變矽層1503在作為主光罩層之層1307上磊晶生長(例如,200埃)後之晶圓1101。
在某些實施例中,藉由離子1111注入空穴可在區域1115中提供一較在區域1113中更鬆弛之矽鍺層。舉例而言,層1307於區域1115中之部分相對於層1307於P-通道區域1113中之部分更為鬆弛。在一鍺原子以1e13/平方公分之劑量及40 KeV之能量植入之實施例中,植入區域之鬆弛自32%(未植入)增加至52%(已植入)。
因此,區域1115之應變矽層1503具有一較區域1113中層1503之應變更高之拉應變,此乃因層1307在區域1115中較在區域1113中相對更鬆弛。區別應變之能力可因N-通道元件及P-通道元件之通道區域具有不同之拉應力而使一電路中之彼等元件具有更佳之性能。
圖16係在P-通道區域1113中形成P-通道電晶體1603且在
區域1115中形成N-通道電晶體1605後之晶圓1101之局部側視圖。電晶體1603包括一閘極1611、一側壁間隔層1613、一閘極氧化物層1612及形成於層1503及1307中之源/汲極區域1617及1619。電晶體1603亦包括一位於層1503中閘極1611下之通道區域。電晶體1605包括一閘極1625、一側壁間隔層1627、一閘極氧化物層1622及形成於層1503及1307中之源/汲極區域1621及1623。電晶體1605亦包括一位於層1503中閘極1625下之通道區域1620。一隔離渠溝絕緣體1607係位於區域1113與區域1115之間。晶圓1101包括其他未圖示之N-通道區域及P-通道區域。其他實施例之電晶體可具有其他構造。
在其他實施例中,可在該凝結製程期間遮罩N-通道區域或P-通道區域之一。因此,在該凝結製程期間,僅消耗層1107之所選擇部分(未遮罩區域內之諸部分)。在其他實施例中,隨後將曝光其他開始時已遮罩之區域(例如,1113或1115)並遮罩開始時未遮罩之區域(例如,1113或1115)。然後,在隨後未遮罩區域上實施第二次凝結作業。因此,藉由針對每一區域之單獨凝結製程可進一步區別區域1113中層1503之應變及區域1115中層1503之應變。
在本發明之一態樣中,一方法包括提供一晶圓。該晶圓具有絕緣體上半導體(SOI)構造。該晶圓包括一包含鍺及矽之第一半導體層。該方法包括使含氯氣體流過晶圓,且同時加熱該晶圓並在該氣體流過後在該第一半導體層上形成一包含矽之第二半導體層。
在本發明之另一態樣中,一方法包括提供一包含一第一半導體層之晶圓。該第一半導體層包括一第一類及一第二類原子。該方法包括在該晶圓上實施一凝結製程。實施該凝結製程可消耗該第一半導體層之一部分。實施該凝結製程包括使一含氯氣體流經該晶圓。實施該凝結製程可在該第一半導體層之其餘部分上形成一包括該第二類原子之層。該方法進一步包括去除包含該第二類原子之層及在去除該層後在其餘部分上形成一第二半導體層。該第二半導體層包括該第二類原子。
在本發明之再一態樣中,一方法包括提供一晶圓。該晶圓具有一絕緣體上半導體(SOI)構造。該晶圓包括一包含矽及鍺之第一半導體層。該方法進一步包括實施一凝結製程。實施該凝結製程可消耗該第一半導體層之一部分。該方法亦包括使一含氯氣體流過該晶圓,且同時在實施該凝結製程後加熱該晶圓。該方法進一步包括在該氣體流過後在該第一半導體層之其餘部分上形成一第二半導體層。
儘管本文已顯示及闡述本發明之具體實施例,但彼等熟諳此項技術者應瞭解,基於本發明之教示,可對本發明做進一步之改變及修改而不背離本發明及其更寬泛之態樣,且因此,隨附申請專利範圍欲將所有該等歸屬於本發明之真實精神及範疇內之改變及修飾涵蓋於其範圍內。
101‧‧‧晶圓
103‧‧‧層
105‧‧‧絕緣層
107‧‧‧層
113‧‧‧P-通道區域
203‧‧‧層
205‧‧‧層
301‧‧‧晶格
305‧‧‧隙間鍺原子
307‧‧‧隙間鍺原子
311‧‧‧隙間矽原子
313‧‧‧晶格點
315‧‧‧晶格點
401‧‧‧晶圓
403‧‧‧層
405‧‧‧絕緣層
407‧‧‧層
409‧‧‧層
501‧‧‧晶格
503‧‧‧空穴
505‧‧‧空穴
507‧‧‧隙間鍺原子
603‧‧‧層
604‧‧‧層
701‧‧‧晶圓
706‧‧‧層
707‧‧‧層
709‧‧‧層
801‧‧‧晶圓
803‧‧‧層
805‧‧‧層
807‧‧‧層
809‧‧‧氮
811‧‧‧頂部部分
905‧‧‧層
907‧‧‧底部部分
1001‧‧‧晶圓
1003‧‧‧主光罩層
1005‧‧‧層
1007‧‧‧層
1009‧‧‧層
1101‧‧‧晶圓
1103‧‧‧矽基板
1105‧‧‧絕緣體
1106‧‧‧層
1107‧‧‧層
1109‧‧‧光阻
1111‧‧‧離子
1113‧‧‧P-通道區域
1115‧‧‧N-通道區域
1203‧‧‧區
1305‧‧‧氧化物層
1307‧‧‧層
1503‧‧‧層
1603‧‧‧電晶體
1605‧‧‧電晶體
1607‧‧‧絕緣體
1611‧‧‧閘極
1612‧‧‧閘極氧化物層
1613‧‧‧側壁間隔層
1614‧‧‧通道區域
1617‧‧‧汲極區域
1619‧‧‧汲極區域
1620‧‧‧通道區域
1621‧‧‧汲極區域
1622‧‧‧閘極氧化物層
1623‧‧‧汲極區域
1625‧‧‧閘極
1627‧‧‧側壁間隔層
彼等熟諳此項技術者參照隨附圖可更加清楚地理解本發明及其諸多目的、特徵及優點。
圖1係一先前技術晶圓之局部側視圖。
圖2係一先前技術晶圓之局部側視圖。
圖3係一先前技術主光罩層晶格之局部二維視圖。
圖4係一本發明一實施例之晶圓在其一製造階段期間之局部側視圖。
圖5係一本發明之主光罩層晶格之局部二維視圖。
圖6係一本發明一實施例之晶圓在其另一製造階段期間之局部側視圖。
圖7係一本發明另一實施例之晶圓在其一製造階段期間之局部側視圖。
圖8係一本發明再一實施例之晶圓在其一製造階段期間之局部側視圖。
圖9係一本發明另一實施例之晶圓在其一製造階段期間之局部側視圖。
圖10係一本發明一實施例之晶圓在其一製造階段期間之局部側視圖。
圖11係一本發明另一實施例之晶圓在其一製造階段期間之局部側視圖。
圖12係一本發明再一實施例之晶圓在其另一製造階段期間之局部側視圖。
圖13係一本發明另一實施例之晶圓在其再一製造階段期間之局部側視圖。
圖14係一本發明另一實施例之晶圓在其另一製造階段期間之局部側視圖。
圖15係一本發明另一實施例之晶圓在其另一製造階段期間之局部側視圖。
圖16係一本發明另一實施例之晶圓在其另一製造階段期間之局部側視圖。
除非另外說明,否則不同圖式中使用的相同參考符號皆表示相同物項。
401‧‧‧晶圓
405‧‧‧絕緣層
407‧‧‧層
603‧‧‧層
604‧‧‧氧化矽層
Claims (17)
- 一種用於形成一應變半導體層之方法,其包括:提供一晶圓,該晶圓具有一絕緣體上半導體(SOI)構造,該晶圓包括一包含鍺及矽之第一半導體層;使一含氯氣體流過該晶圓且同時加熱該晶圓;在該氣體流過後,在該第一半導體層上形成一包含矽之第二半導體層。
- 如請求項1之方法,其中該含氯氣體之流過係在一凝結製程期間實施。
- 如請求項2之方法,其中該凝結製程消耗該第一半導體層之一部分。
- 如請求項3之方法,其中該凝結製程包括一氧化製程,其中該氧化製程包括在該第一半導體層上形成一氧化物。
- 如請求項4之方法,其進一步包括:在形成該第二半導體層之前去除該氧化物。
- 如請求項2之方法,其中該凝結製程消耗該第一半導體層之一部分,其中形成該第二半導體層包括使用該第一半導體層之一其餘部分作為一主光罩層。
- 如請求項1之方法,其中該含氯氣體之流過係作為該晶圓之部分後烘焙實施。
- 如請求項1之方法,其進一步包括:在形成該第二半導體層之前,在該晶圓上實施一凝結製程;其中該含氯氣體之流過係在實施該凝結製程之後實 施。
- 如請求項1之方法,其中使該含氯氣體流過該晶圓且同時加熱該晶圓包括以1100℃或以下之溫度加熱該晶圓。
- 如請求項1之方法,其進一步包括:形成一具有一通道區域之電晶體,其中該通道區域之至少一部分係位於該第二半導體層內。
- 如請求項1之方法,其中該含氯氣體之流過包括該含氯氣體以0.1至10%之濃度流過。
- 一種用於形成一應變半導體層之方法,其包括:提供一包含一第一半導體層之晶圓,該第一半導體層包括一第一類及一第二類原子;在該晶圓上實施一凝結製程,該凝結製程之實施消耗該第一半導體層之一部分,其中該凝結製程之實施包括使一含氯氣體流過該晶圓,該凝結製程之實施在該第一半導體層之一其餘部分上形成一包含該第二類原子之層;去除該包含該第二類原子之層;在該去除後在該其餘部分上形成一第二半導體層,該第二半導體層包含該第二類原子。
- 如請求項12之方法,其進一步包括:形成一具有一通道區域之電晶體,其中該通道區域之至少一部分係位於該第二半導體層內。
- 一種用於形成一應變半導體層之方法,其包括:提供一晶圓,該晶圓具有一絕緣體上半導體(SOI)構造,該晶圓包括一包含矽及鍺之第一半導體層; 實施一凝結製程,該凝結製程之實施消耗該第一半導體層之一部分;在實施該凝結製程後,使一含氯氣體流過該晶圓且同時加熱該晶圓;在該氣體流過後,在該第一半導體層之一其餘部分上形成一第二半導體層。
- 如請求項14之方法,其中形成一第二半導體層包括使用該其餘部分作為一主光罩層。
- 如請求項14之方法,其進一步包括:形成一具有一通道區域之電晶體,其中該通道區域之至少一部分係位於該第二半導體層內。
- 一種用於形成一應變半導體層之方法,其包括:提供一包含矽及鍺且在一晶圓之一絕緣層上具有一晶體結構之第一半導體層;在該晶體結構上形成一氧氮化物層,其中該形成包括使用一製程來消耗該第一半導體層之一部分,且其中該製程包含使一含氯氣體流過該晶圓並同時加熱該晶圓;去除該氧氮化物層;在去除該氧氮化物層後,在該晶體結構上形成一包含矽之第二半導體層。
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Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
US7598513B2 (en) * | 2003-06-13 | 2009-10-06 | Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University, A Corporate Body Organized Under Arizona Law | SixSnyGe1-x-y and related alloy heterostructures based on Si, Ge and Sn |
US7078300B2 (en) * | 2003-09-27 | 2006-07-18 | International Business Machines Corporation | Thin germanium oxynitride gate dielectric for germanium-based devices |
FR2861497B1 (fr) * | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7217949B2 (en) * | 2004-07-01 | 2007-05-15 | International Business Machines Corporation | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) |
EP1851789B1 (en) * | 2005-02-24 | 2013-05-01 | Soitec | Thermal oxidation of a sige layer and applications thereof |
US20060228492A1 (en) * | 2005-04-07 | 2006-10-12 | Sumco Corporation | Method for manufacturing SIMOX wafer |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
WO2007053381A1 (en) * | 2005-10-31 | 2007-05-10 | Advanced Micro Devices, Inc. | Technique for strain engineering in si-based transistors by using embedded semiconductor layers including atoms with high covalent radius |
DE102005051994B4 (de) * | 2005-10-31 | 2011-12-01 | Globalfoundries Inc. | Verformungsverfahrenstechnik in Transistoren auf Siliziumbasis unter Anwendung eingebetteter Halbleiterschichten mit Atomen mit einem großen kovalenten Radius |
US7265004B2 (en) * | 2005-11-14 | 2007-09-04 | Freescale Semiconductor, Inc. | Electronic devices including a semiconductor layer and a process for forming the same |
FR2898215B1 (fr) * | 2006-03-01 | 2008-05-16 | Commissariat Energie Atomique | Procede de fabrication d'un substrat par condensation germanium |
FR2899017A1 (fr) * | 2006-03-21 | 2007-09-28 | St Microelectronics Sa | Procede de realisation d'un transistor a canal comprenant du germanium |
US7882382B2 (en) * | 2006-06-14 | 2011-02-01 | International Business Machines Corporation | System and method for performing computer system maintenance and service |
US7629220B2 (en) | 2006-06-30 | 2009-12-08 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device and structure thereof |
FR2910179B1 (fr) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
US7560354B2 (en) * | 2007-08-08 | 2009-07-14 | Freescale Semiconductor, Inc. | Process of forming an electronic device including a doped semiconductor layer |
FR2922359B1 (fr) * | 2007-10-12 | 2009-12-18 | Commissariat Energie Atomique | Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire |
US20090191468A1 (en) * | 2008-01-29 | 2009-07-30 | International Business Machines Corporation | Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features |
US20090250760A1 (en) * | 2008-04-02 | 2009-10-08 | International Business Machines Corporation | Methods of forming high-k/metal gates for nfets and pfets |
US20090289280A1 (en) * | 2008-05-22 | 2009-11-26 | Da Zhang | Method for Making Transistors and the Device Thereof |
US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
US7975246B2 (en) * | 2008-08-14 | 2011-07-05 | International Business Machines Corporation | MEEF reduction by elongation of square shapes |
US8440547B2 (en) * | 2009-02-09 | 2013-05-14 | International Business Machines Corporation | Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering |
FR2947098A1 (fr) * | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
US8623728B2 (en) | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
US8647439B2 (en) | 2012-04-26 | 2014-02-11 | Applied Materials, Inc. | Method of epitaxial germanium tin alloy surface preparation |
US9231063B2 (en) | 2014-02-24 | 2016-01-05 | International Business Machines Corporation | Boron rich nitride cap for total ionizing dose mitigation in SOI devices |
TWI531071B (zh) * | 2014-07-08 | 2016-04-21 | Univ Nat Central | Fabrication method of gold - oxygen half - gate stacking structure |
US9305781B1 (en) | 2015-04-30 | 2016-04-05 | International Business Machines Corporation | Structure and method to form localized strain relaxed SiGe buffer layer |
KR20170036966A (ko) | 2015-09-24 | 2017-04-04 | 삼성전자주식회사 | 반도체 소자의 제조하는 방법 |
US10541172B2 (en) | 2016-08-24 | 2020-01-21 | International Business Machines Corporation | Semiconductor device with reduced contact resistance |
US9799618B1 (en) | 2016-10-12 | 2017-10-24 | International Business Machines Corporation | Mixed UBM and mixed pitch on a single die |
US10930793B2 (en) * | 2017-04-21 | 2021-02-23 | International Business Machines Corporation | Bottom channel isolation in nanosheet transistors |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3912559A (en) * | 1971-11-25 | 1975-10-14 | Suwa Seikosha Kk | Complementary MIS-type semiconductor devices and methods for manufacturing same |
US4851257A (en) * | 1987-03-13 | 1989-07-25 | Harris Corporation | Process for the fabrication of a vertical contact |
US5461243A (en) | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
US5534713A (en) | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
DE59707274D1 (de) | 1996-09-27 | 2002-06-20 | Infineon Technologies Ag | Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung |
US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
US5943565A (en) | 1997-09-05 | 1999-08-24 | Advanced Micro Devices, Inc. | CMOS processing employing separate spacers for independently optimized transistor performance |
US5846857A (en) | 1997-09-05 | 1998-12-08 | Advanced Micro Devices, Inc. | CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance |
US6124627A (en) | 1998-12-03 | 2000-09-26 | Texas Instruments Incorporated | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region |
US6259138B1 (en) | 1998-12-18 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith |
US6369438B1 (en) | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
JP3884203B2 (ja) | 1998-12-24 | 2007-02-21 | 株式会社東芝 | 半導体装置の製造方法 |
JP2001036054A (ja) | 1999-07-19 | 2001-02-09 | Mitsubishi Electric Corp | Soi基板の製造方法 |
US6339232B1 (en) | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
KR100392166B1 (ko) | 2000-03-17 | 2003-07-22 | 가부시끼가이샤 도시바 | 반도체 장치의 제조 방법 및 반도체 장치 |
JP4827324B2 (ja) * | 2000-06-12 | 2011-11-30 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6524935B1 (en) | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
US6890835B1 (en) | 2000-10-19 | 2005-05-10 | International Business Machines Corporation | Layer transfer of low defect SiGe using an etch-back process |
KR100720095B1 (ko) * | 2000-11-07 | 2007-05-18 | 삼성전자주식회사 | 박막 트랜지스터 어레이 기판 및 그 제조 방법 |
US7312485B2 (en) | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
US20020100942A1 (en) | 2000-12-04 | 2002-08-01 | Fitzgerald Eugene A. | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US20020168802A1 (en) * | 2001-05-14 | 2002-11-14 | Hsu Sheng Teng | SiGe/SOI CMOS and method of making the same |
US6855436B2 (en) * | 2003-05-30 | 2005-02-15 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
JP3647777B2 (ja) * | 2001-07-06 | 2005-05-18 | 株式会社東芝 | 電界効果トランジスタの製造方法及び集積回路素子 |
JP2003031495A (ja) | 2001-07-12 | 2003-01-31 | Hitachi Ltd | 半導体装置用基板の製造方法および半導体装置の製造方法 |
US6475870B1 (en) | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
EP1428262A2 (en) | 2001-09-21 | 2004-06-16 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US6621131B2 (en) | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
US6515335B1 (en) | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
US6562703B1 (en) | 2002-03-13 | 2003-05-13 | Sharp Laboratories Of America, Inc. | Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content |
US6743651B2 (en) | 2002-04-23 | 2004-06-01 | International Business Machines Corporation | Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen |
US6638802B1 (en) | 2002-06-20 | 2003-10-28 | Intel Corporation | Forming strained source drain junction field effect transistors |
JP3873012B2 (ja) * | 2002-07-29 | 2007-01-24 | 株式会社東芝 | 半導体装置の製造方法 |
US6955952B2 (en) | 2003-03-07 | 2005-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement |
US7026249B2 (en) | 2003-05-30 | 2006-04-11 | International Business Machines Corporation | SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth |
US7049660B2 (en) | 2003-05-30 | 2006-05-23 | International Business Machines Corporation | High-quality SGOI by oxidation near the alloy melting temperature |
JP2004363199A (ja) * | 2003-06-02 | 2004-12-24 | Sumitomo Mitsubishi Silicon Corp | 半導体基板の製造方法 |
KR20060056331A (ko) * | 2003-07-23 | 2006-05-24 | 에이에스엠 아메리카, 인코포레이티드 | 절연체-상-실리콘 구조 및 벌크 기판 상의 SiGe 증착 |
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US7029980B2 (en) | 2006-04-18 |
US20050070057A1 (en) | 2005-03-31 |
TW200513791A (en) | 2005-04-16 |
JP2007507109A (ja) | 2007-03-22 |
JP4690326B2 (ja) | 2011-06-01 |
US20050070056A1 (en) | 2005-03-31 |
US7056778B2 (en) | 2006-06-06 |
CN1926660B (zh) | 2011-06-22 |
US20050070053A1 (en) | 2005-03-31 |
US7208357B2 (en) | 2007-04-24 |
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