JP2008211212A - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法 Download PDFInfo
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- JP2008211212A JP2008211212A JP2008036209A JP2008036209A JP2008211212A JP 2008211212 A JP2008211212 A JP 2008211212A JP 2008036209 A JP2008036209 A JP 2008036209A JP 2008036209 A JP2008036209 A JP 2008036209A JP 2008211212 A JP2008211212 A JP 2008211212A
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Classifications
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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Abstract
【解決手段】タングステン膜を含むゲート電極7A、7B、7C上に窒化シリコン膜11を形成する際、CVD装置のチャンバ内をタングステンの酸化物が還元される雰囲気にし、チャンバ内にアンモニアを供給し続けながら、ウエハ1を600℃以上の温度で昇温する。次に、チャンバ内にアンモニアとモノシランとを供給し、これらのガスを反応させることによって窒化シリコン膜11を堆積する。次に、モノシランの供給を止め、チャンバ内にアンモニアのみを供給し続けながらウエハ1を400℃まで降温した後、チャンバ内を窒素で置換し、ウエハをアンロードする。
【選択図】図26
Description
(a)半導体基板上に、前記フラッシュメモリの第1ゲート絶縁膜を形成する工程;
(b)前記第1ゲート絶縁膜上に第1多結晶シリコン膜を形成する工程;
(c)前記(b)工程後に、前記第1多結晶シリコン膜を、第1方向に延在するようにパターニングする工程;
(d)前記(b)工程後に、前記第1多結晶シリコン膜上に、前記フラッシュメモリの第2ゲート絶縁膜を形成する工程;
(e)前記第2ゲート絶縁膜上に、第2多結晶シリコン膜、窒化タングステン膜およびタングステン膜を順次形成する工程;
(f)前記(e)工程後に、前記タングステン膜、前記窒化タングステン膜および前記第2多結晶シリコン膜が前記第1方向と直交する第2方向に延在するように、前記タングステン膜、前記窒化タングステン膜、前記第2多結晶シリコン膜、前記第2ゲート絶縁膜および前記第1多結晶シリコン膜を順次パターニングすることで、前記第1多結晶シリコン膜からなる前記フラッシュメモリのフローティングゲートを形成し、且つ、前記タングステン膜、前記窒化タングステン膜および前記第2多結晶シリコン膜からなる前記フラッシュメモリのコントロールゲートを形成する工程;
(g)前記(f)工程後に、前記タングステン膜の酸化物に対して還元性雰囲気の条件下で、前記半導体基板を摂氏600度以上の第1温度まで昇温する工程;
(h)前記(g)工程後に、前記第1温度において、化学気相堆積によって窒化シリコン膜を形成する工程;
(i)前記(h)工程後に、前記タングステン膜の酸化物に対して還元性雰囲気の条件下で、摂氏500度未満の第2温度まで降温する工程;
(j)前記(i)工程後に、前記還元性雰囲気から窒素ガス雰囲気に切り替える工程。
図1は、本実施形態のDRAM(Dynamic Random Access Memory)が形成された半導体チップ1Aの全体平面図である。長方形の半導体チップ1Aの主面には、例えば256Mbit(メガビット)の記憶容量を有するDRAMが形成されている。このDRAMは、主として複数のメモリアレイ(MARY)からなる記憶部とそれらの周囲に配置された周辺回路部PCとによって構成されている。半導体チップ1Aの中央部には、ボンディングワイヤなどの接続端子が接続される複数のボンディングパッドBPが1列に配置されている。
本実施形態は、ロジック混載DRAMに適用したものであり、その製造方法の一例を、図38〜図45を用いて工程順に説明する。なお、製造方法を示す各断面図の左側部分はDRAMのメモリアレイの一部を示し、右側部分はロジック部の一部を示している。
前記実施の形態2では、WNX膜24と多結晶シリコン膜14n、14pとの間にアモルファスシリコン膜34aを介在させることによって、WNX膜24と多結晶シリコン膜14n、14pとの接触抵抗を低減したが、本実施の形態では、WNX膜24と多結晶シリコン膜14n、14pとの間に薄い膜厚のW膜62を介在させることによって、WNX膜24と多結晶シリコン膜14n、14pとの接触抵抗を低減する。
本実施形態は、nチャネル型MISFETとpチャネル型MISFETで回路を構成するCMOSロジックLSIに適用したものであり、その製造方法の一例を、図52〜図56を用いて工程順に説明する。
前記実施の形態4では、不純物のイオン注入法によって多結晶シリコン膜14nの表面領域を低抵抗化したが、次のような方法で多結晶シリコン膜14nの表面領域を低抵抗化することもできる。
本実施形態は、フラッシュメモリに適用したものであり、その製造方法の一例を、図63〜図75を用いて工程順に説明する。
1A 半導体チップ
2 素子分離溝
3 p型ウエル
4 n型ウエル
5 酸化シリコン膜
6 ゲート絶縁膜
7A〜7G ゲート電極
8 窒化シリコン膜
9 n型半導体領域(ソース、ドレイン)
10 p-型半導体領域
11 窒化シリコン膜
11c サイドウォールスペーサ
12 n+型半導体領域(ソース、ドレイン)
13 p+型半導体領域(ソース、ドレイン)
14a アモルファスシリコン膜
14n、14p 多結晶シリコン膜
15 層間絶縁膜
16、17 コンタクトホール
18 プラグ
19 酸化シリコン膜
20 スルーホール
21、22 コンタクトホール
23 プラグ
24 WNX膜
25 W膜
26 フォトレジスト膜
27 酸化物(WOX)
28、29 フォトレジスト膜
30〜33 配線
34a アモルファスシリコン膜
40 層間絶縁膜
41 多結晶シリコン膜
42 サイドウォールスペーサ
43 スルーホール
44 プラグ
45 窒化シリコン膜
46 酸化シリコン膜
47 溝
48 下部電極
49 容量絶縁膜
50 上部電極
51 酸化シリコン膜
60〜63 フォトレジスト膜
64 n型多結晶シリコン膜
65 W膜
66n 多結晶シリコン膜
67 ONO膜
68 フローティングゲート電極
69 コントロールゲート電極
70 n型半導体領域(ソース、ドレイン)
100 枚葉式酸化炉
101 チャンバ
103 均熱リング
104 サセプタ
105 支持アーム
106 熱電対
107 ハロゲンランプ
108 ガス導入管
109 貫通孔
110 隔壁
111 排気管
140 ガス生成装置
141 反応器
142 コイル
143 ヒータ
144a、144b、144c ガス貯留槽
145 配管
146a、146b、146c マスフローコントローラ
147a、147b、147c 開閉バルブ
148 希釈ライン
150 バッチ式縦型酸化炉
151 チャンバ
152 ヒータ
153 石英ボート
154 ガス導入管
155 排気管
BL ビット線
BP ボンディングパッド
C 情報蓄積用容量素子
L アクティブ領域
MARY メモリアレイ
PC 周辺回路部
Qn nチャネル型MISFET
Qp pチャネル型MISFET
Qt メモリセル選択用MISFET
WL ワード線
Claims (8)
- フラッシュメモリを有する半導体集積回路装置の製造方法であって、
(a)半導体基板上に、前記フラッシュメモリの第1ゲート絶縁膜を形成する工程;
(b)前記第1ゲート絶縁膜上に第1多結晶シリコン膜を形成する工程;
(c)前記(b)工程後に、前記第1多結晶シリコン膜を、第1方向に延在するようにパターニングする工程;
(d)前記(b)工程後に、前記第1多結晶シリコン膜上に、前記フラッシュメモリの第2ゲート絶縁膜を形成する工程;
(e)前記第2ゲート絶縁膜上に、第2多結晶シリコン膜、窒化タングステン膜およびタングステン膜を順次形成する工程;
(f)前記(e)工程後に、前記タングステン膜、前記窒化タングステン膜および前記第2多結晶シリコン膜が前記第1方向と直交する第2方向に延在するように、前記タングステン膜、前記窒化タングステン膜、前記第2多結晶シリコン膜、前記第2ゲート絶縁膜および前記第1多結晶シリコン膜を順次パターニングすることで、前記第1多結晶シリコン膜からなる前記フラッシュメモリのフローティングゲートを形成し、且つ、前記タングステン膜、前記窒化タングステン膜および前記第2多結晶シリコン膜からなる前記フラッシュメモリのコントロールゲートを形成する工程;
(g)前記(f)工程後に、前記タングステン膜の酸化物に対して還元性雰囲気の条件下で、前記半導体基板を摂氏600度以上の第1温度まで昇温する工程;
(h)前記(g)工程後に、前記第1温度において、化学気相堆積によって窒化シリコン膜を形成する工程;
(i)前記(h)工程後に、前記タングステン膜の酸化物に対して還元性雰囲気の条件下で、摂氏500度未満の第2温度まで降温する工程;
(j)前記(i)工程後に、前記還元性雰囲気から窒素ガス雰囲気に切り替える工程。 - 請求項1記載の半導体集積回路装置の製造方法において、
前記(f)工程後であって、且つ、前記(g)工程前に、
(k)前記タングステン膜の酸化物に対して還元性雰囲気の条件下で、前記半導体基板を摂氏600度以上の第3温度まで昇温する工程;
(l)前記(k)工程後に、水素と、触媒によって酸素および水素から合成された水分とを含む混合ガス雰囲気中において、前記タングステン膜を酸化することなく、前記半導体基板を前記第3温度で酸化処理する工程;
(m)前記(l)工程の後、濃度30重量%の過酸化水素水を100%とした場合に、過酸化水素を体積比で0.3%以上含まない水または薬液であって、pH6.5以上であり、且つ、pH12未満の水または薬液により、前記半導体基板を洗浄する工程;
を有することを特徴とする半導体集積回路装置の製造方法。 - 請求項2記載の半導体集積回路装置の製造方法において、
前記第3温度は、摂氏800℃以上であることを特徴とする半導体集積回路装置の製造方法。 - 請求項2または3記載の半導体集積回路装置の製造方法において、
前記(l)工程は、大気圧以下であり、且つ、1300Pa以上の圧力の条件下で行われることを特徴とする半導体集積回路装置の製造方法。 - 請求項2〜4のいずれか1項に記載の半導体集積回路装置の製造方法において、
前記(l)工程における混合ガスは、窒素ガス、アルゴンガスまたはヘリウムガスを含むことを特徴とする半導体集積回路装置の製造方法。 - 請求項1〜5のいずれか1項に記載の半導体集積回路装置の製造方法において、
前記(m)工程の後、イオン注入法によって、前記半導体基板に前記フラッシュメモリのソース領域およびドレイン領域を形成する工程をさらに有することを特徴とする半導体集積回路装置の製造方法。 - 請求項1〜6のいずれか1項に記載の半導体集積回路装置の製造方法において、
前記第1ゲート絶縁膜は、酸化シリコン膜で形成されていることを特徴とする半導体集積回路装置の製造方法。 - 請求項1〜7のいずれか1項に記載の半導体集積回路装置の製造方法において、
前記第2ゲート絶縁膜は、酸化シリコン膜および窒化シリコン膜の積層膜で形成されていることを特徴とする半導体集積回路装置の製造方法。
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- 2001-10-31 CN CNB018229441A patent/CN1290197C/zh not_active Expired - Fee Related
- 2001-10-31 KR KR10-2004-7020408A patent/KR20050004924A/ko not_active Application Discontinuation
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JP2020522877A (ja) * | 2017-06-05 | 2020-07-30 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | ワードライン抵抗を低下させる方法 |
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US7300833B2 (en) | 2007-11-27 |
TW536753B (en) | 2003-06-11 |
US7144766B2 (en) | 2006-12-05 |
US20060009046A1 (en) | 2006-01-12 |
KR20050004924A (ko) | 2005-01-12 |
CN100447980C (zh) | 2008-12-31 |
US20070048917A1 (en) | 2007-03-01 |
US7049187B2 (en) | 2006-05-23 |
CN1505840A (zh) | 2004-06-16 |
CN1290197C (zh) | 2006-12-13 |
JPWO2002073696A1 (ja) | 2004-07-08 |
KR20030080239A (ko) | 2003-10-11 |
JP4109118B2 (ja) | 2008-07-02 |
KR100653796B1 (ko) | 2006-12-05 |
JP4607197B2 (ja) | 2011-01-05 |
CN1941324A (zh) | 2007-04-04 |
US20040063276A1 (en) | 2004-04-01 |
WO2002073696A1 (fr) | 2002-09-19 |
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