JP2008177546A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2008177546A JP2008177546A JP2007315322A JP2007315322A JP2008177546A JP 2008177546 A JP2008177546 A JP 2008177546A JP 2007315322 A JP2007315322 A JP 2007315322A JP 2007315322 A JP2007315322 A JP 2007315322A JP 2008177546 A JP2008177546 A JP 2008177546A
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】チャネル形成領域、第1の低濃度不純物領域、第2の低濃度不純物領域、及び、シリサイド層を含む高濃度不純物領域を有する島状半導体膜と、ゲート絶縁膜と、前記ゲート絶縁膜を介して、前記チャネル形成領域及び第1の低濃度不純物領域と重なっている第1のゲート電極と、前記ゲート絶縁膜を介して、前記チャネル形成領域と重なっている第2のゲート電極と、前記第1のゲート電極及び前記第2のゲート電極の側面に形成されたサイドウォールとを有し、前記ゲート絶縁膜は、前記第2の低濃度不純領域上の膜厚が、それ以外の領域の膜厚よりも薄い半導体装置に関連する。
【選択図】図2
Description
以下に、本実施の形態による半導体装置の作製方法を、図1(A)〜図1(D)、図2(A)〜図2(H)、図6(A)〜図6(B)を用いて説明する。
本実施の形態では、Loff領域のみを有する半導体装置の作製方法を、図3(A)〜図3(D)に示す。また、本実施の形態において、実施の形態1と同じものについては同じ符号を用い、詳細な説明を省略する。
本実施の形態では、実施の形態2とは別の、Loff領域のみを有する半導体装置の作製方法を、図4(A)〜図4(C)及び図5(A)〜図5(D)に示す。また、本実施の形態において、実施の形態1及び実施の形態2と同じものについては同じ符号を用い、詳細な説明を省略する。
本実施の形態では、本発明を用いてCPU(中央演算装置:Central Processing Unit)を作製した例を、図7(A)〜図7(B)、図8、図9、図10(A)〜図10(C)を用いて説明する。本実施の形態において、実施の形態1〜実施の形態3と同じものについては同じ符号を用い、詳細な説明を省略する。
本実施の形態は、本発明のTFTを有する、ICを用いた無線通信が可能な半導体装置を作成する例を、図11、図12、図13、図14、図15を用いて説明する。
20nm+(30nm×1.6)=68nm
112 下地絶縁膜
113 島状半導体膜
114 ゲート絶縁膜
115 導電膜
116 導電膜
117 レジスト
118 導電膜
119 レジスト
120 ゲート電極
121 レジスト
122 ゲート電極
123 レジスト
124a 低濃度不純物領域
124b 低濃度不純物領域
125a 低濃度不純物領域
125b 低濃度不純物領域
126 チャネル形成領域
127 不純物元素
128 サイドウォール
129 ゲート絶縁膜
130 金属膜
131 シリサイド層
132 不純物元素
133a 高濃度不純物領域
133b 高濃度不純物領域
134a 低濃度不純物領域
134b 低濃度不純物領域
135 層間絶縁膜
136 配線
136a 電極または配線
136b 電極または配線
136c 電極または配線
137a 低濃度不純物領域
137b 低濃度不純物領域
150 ゲート電極
152a 低濃度不純物領域
152b 低濃度不純物領域
154a 低濃度不純物領域
154b 低濃度不純物領域
156 チャネル形成領域
158 サイドウォール
159 ゲート絶縁膜
160 ゲート電極
161 ゲート絶縁膜
162 ゲート電極
163 ゲート電極
163a 高濃度不純物領域
163b 高濃度不純物領域
164a 低濃度不純物領域
164a 低濃度不純物領域
165 ゲート絶縁膜
166a 低濃度不純物領域
166b 低濃度不純物領域
167a 高濃度不純物領域
167b 高濃度不純物領域
171 層間絶縁膜
173 導電層
174 導電層
175 薄膜集積回路
181 TFT
182 TFT
183 CMOS回路
360 基板
361 演算回路
362 演算回路用制御回路部
363 命令解析部
364 割り込み制御部
365 タイミング制御部
366 レジスタ
367 レジスタ制御部
368 バスインターフェース
369 ROM
370 基板
371 画素部
372 走査線駆動回路
373 信号線駆動回路
374 CPU
375 コントロール回路
380 ROMインターフェース
381 CLK1
382 CLK2
384 バンプ
385 プラスチック
387 プリント基板
388 ワイヤ
390 基板
391 薄膜トランジスタアレイ
392 電極
393 配線
394 接続端子
395 樹脂
397 プリント基板
398 異方性導電膜
399 FPC
401 TFT
402 TFT
403 TFT
404 TFT
411 メモリセルアレイ
414 出力線
415 列デコーダ
416 行デコーダ
417 制御線
422 高電圧電源
423 低電圧電源
424 ビット線(データ線)
425 ビット線(データ線)
427 配線
428 配線
431 電源線
432 配線
433 電源線
434 配線
441 nチャネル型TFT
442 pチャネル型TFT
511 基板
512 下地絶縁膜
520 ゲート電極
522 ゲート電極
524a 低濃度不純物領域
524b 低濃度不純物領域
526 チャネル形成領域
528 サイドウォール
529 ゲート絶縁膜
531 シリサイド層
533a 高濃度不純物領域
533b 高濃度不純物領域
534a 低濃度不純物領域
534b 低濃度不純物領域
535 層間絶縁膜
536 電極または配線
536a 電極または配線
536c 電極または配線
536d 電極または配線
536e 電極または配線
550 ゲート電極
552 ゲート電極
554a 低濃度不純物領域
556 チャネル形成領域
558 サイドウォール
559 ゲート絶縁膜
563a 高濃度不純物領域
563b 高濃度不純物領域
564a 低濃度不純物領域
564b 低濃度不純物領域
571 層間絶縁膜
573 導電層
574 導電層
577 導電層
578 導電層
579 空隙
581 TFT
582 TFT
900 マスクROM
901 信号出力制御回路
902 CRC回路
903 クロック発生回路
904 コード抽出回路
905 コード判定回路
906 整流回路
907 復調回路
908 アナログアンプ
909 変調回路
911 リセット回路
912 保持容量
913 整流回路
914 高周波回路
915 電源回路
917 アンテナ
920 メモリセルアレイ
921 列デコーダ
922 行デコーダ
931 半導体装置
Claims (9)
- チャネル形成領域、第1の低濃度不純物領域、第2の低濃度不純物領域、及び、シリサイド層を含む高濃度不純物領域を有する島状半導体膜と、
ゲート絶縁膜と、
前記ゲート絶縁膜を介して、前記チャネル形成領域及び第1の低濃度不純物領域と重なっている第1のゲート電極と、
前記ゲート絶縁膜を介して、前記チャネル形成領域と重なっている第2のゲート電極と、
前記第1のゲート電極及び前記第2のゲート電極の側面に形成されたサイドウォールと、
を有し、
前記ゲート絶縁膜は、前記第2の低濃度不純領域上の膜厚が、それ以外の領域の膜厚よりも薄いことを特徴とする半導体装置。 - 請求項1において、
前記シリサイド層は、ニッケル、チタン、コバルト、白金、もしくはこれら元素のうち少なくとも2種類を含むことを特徴とする半導体装置。 - チャネル形成領域、低濃度不純物領域、及び、高濃度不純物領域を有する島状半導体膜と、
ゲート絶縁膜と、
前記ゲート絶縁膜を介して、前記チャネル形成領域と重なっているゲート電極と、
前記ゲート電極の側面に形成されたサイドウォールと、
を有し
前記ゲート絶縁膜は、低濃度不純領域上の膜厚が、それ以外の領域の膜厚よりも薄いことを特徴とする半導体装置。 - チャネル形成領域、低濃度不純物領域、及び、シリサイド層を含む高濃度不純物領域を有する島状半導体膜と、
ゲート絶縁膜と、
前記ゲート絶縁膜を介して、前記チャネル形成領域と重なっているゲート電極と、
前記ゲート電極の側面に形成されたサイドウォールと、
を有し、
前記ゲート絶縁膜は、低濃度不純領域上の膜厚が、それ以外の領域の膜厚よりも薄いことを特徴とする半導体装置。 - 請求項4において、
前記シリサイド層は、ニッケル、チタン、コバルト、白金、もしくはこれら元素のうち少なくとも2種類を含むことを特徴とする半導体装置。 - チャネル形成領域、第1の低濃度不純物領域、第2の低濃度不純物領域、及び、高濃度不純物領域を有する島状半導体膜と、
ゲート絶縁膜と、
前記ゲート絶縁膜を介して、前記チャネル形成領域及び第1の低濃度不純物領域と重なっている第1のゲート電極と、
前記ゲート絶縁膜を介して、前記チャネル形成領域と重なっている第2のゲート電極と、
前記第1のゲート電極及び前記第2のゲート電極の側面に形成されたサイドウォールと、
を有し、
前記ゲート絶縁膜は、前記第2の低濃度不純領域上の膜厚が、それ以外の領域の膜厚よりも薄いことを特徴とする半導体装置。 - 基板上に、島状半導体膜を形成し、
前記島状半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に、第1の導電膜及び第2の導電膜を形成し、
前記第2の導電膜をエッチングし、第3の導電膜を形成し、
前記第1の導電膜をエッチングして、第1のゲート電極を形成し、
前記第3の導電膜をエッチングして、第2のゲート電極を形成し、かつ、前記ゲート絶縁膜中の、前記第1のゲート電極の下の領域以外がエッチングされ、前記ゲート絶縁膜の膜厚が薄くなり、
前記第2のゲート電極をマスクとして、前記第1のゲート電極及び前記ゲート絶縁膜を通過させて前記島状半導体膜に不純物元素を添加し、前記島状半導体膜の内、前記第2のゲート電極の下方の領域に、チャネル形成領域を形成し、前記第1のゲート電極と重なる領域に第1の低濃度不純物領域を形成し、前記不純物元素が前記ゲート絶縁膜のみを通過した前記島状半導体膜の両端の領域には、不純物領域が形成され、
前記ゲート絶縁膜、前記第1のゲート電極、及び、前記第2のゲート電極を覆って、絶縁層を形成し、
前記絶縁層をエッチングして、前記第1のゲート電極及び第2のゲート電極の側面に、サイドウォールを形成し、かつ、前記ゲート絶縁膜の前記サイドウォールに覆われていない領域を除去して、前記島状半導体膜の前記サイドウォールに覆われていない領域を露出させ、
前記サイドウォール、前記露出した島状半導体膜を覆って、金属膜を形成し、
加熱処理により前記金属膜と前記露出した島状半導体膜を反応させ、前記露出した島状半導体膜中にシリサイド層を形成し、
前記サイドウォール、前記第1のゲート電極、前記第2のゲート電極をマスクとして、前記島状半導体膜に不純物元素を添加して、前記露出した島状半導体膜に高濃度不純物領域を形成し、前記不純物領域の、前記ゲート絶縁膜及び前記サイドウォールに覆われた領域に、第2の低濃度不純物領域を形成することを特徴とする半導体装置の作製方法。 - 請求項7において、
前記シリサイド層は、ニッケル、チタン、コバルト、白金、もしくはこれら元素のうち少なくとも2種類を含むことを特徴とする半導体装置の作製方法。 - 島状半導体膜を形成し、
前記島状半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に、第1の導電膜及び第2の導電膜を形成し、
前記第2の導電膜をエッチングし、第3の導電膜を形成し、
前記第1の導電膜をエッチングして、第1のゲート電極を形成し、
前記第3の導電膜をエッチングして、第2のゲート電極を形成し、かつ、前記ゲート絶縁膜中の、前記第1のゲート電極の下の領域以外がエッチングされ、前記ゲート絶縁膜の膜厚が薄くなり、
前記第2のゲート電極をマスクとして、前記第1のゲート電極及び前記ゲート絶縁膜を通過させて前記島状半導体膜に不純物元素を添加し、前記島状半導体膜の内、前記第2のゲート電極の下方の領域に、チャネル形成領域を形成し、前記第1のゲート電極と重なる領域に第1の低濃度不純物領域を形成し、前記不純物元素が前記ゲート絶縁膜のみを通過した前記島状半導体膜の両端の領域には、不純物領域が形成され、
前記ゲート絶縁膜、前記第1のゲート電極、及び、前記第2のゲート電極を覆って、絶縁層を形成し、
前記絶縁層をエッチングして、前記第1のゲート電極及び第2のゲート電極の側面に、サイドウォールを形成し、
前記サイドウォール、前記第1のゲート電極、前記第2のゲート電極をマスクとして、前記島状半導体膜に不純物元素を添加して、前記島状半導体膜中の、前記サイドウォールに領域に覆われなかった領域に高濃度不純物領域を形成し、前記不純物領域の、前記ゲート絶縁膜及び前記サイドウォールに覆われた領域に、第2の低濃度不純物領域を形成することを特徴とする半導体装置の作製方法。
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CN101207156B (zh) | 2011-03-23 |
CN101207156A (zh) | 2008-06-25 |
US7705358B2 (en) | 2010-04-27 |
US20080150027A1 (en) | 2008-06-26 |
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