JP2008165960A - Nand型フラッシュメモリ素子のデータ消去方法 - Google Patents
Nand型フラッシュメモリ素子のデータ消去方法 Download PDFInfo
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- JP2008165960A JP2008165960A JP2007293816A JP2007293816A JP2008165960A JP 2008165960 A JP2008165960 A JP 2008165960A JP 2007293816 A JP2007293816 A JP 2007293816A JP 2007293816 A JP2007293816 A JP 2007293816A JP 2008165960 A JP2008165960 A JP 2008165960A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
【解決手段】消去しようとするブロックのメモリセルに第1消去電圧を印加する段階と、第2検証電圧より高い第1検証電圧を用いて前記メモリセルの消去状態を検証する第1検証段階と、前記第1検証段階をパスしていないメモリセルを第1グループに分類し、前記第1検証段階をパスしたメモリセルに対して第2検証電圧で検証する第2検証段階と、前記第2検証電圧に対してパスしたメモリセルを第2グループに分類し、パスしていないメモリセルを第3グループに分類する段階と、前記第1、第2及び第3グループのメモリセルに対してそれぞれ異なるステップ電圧及び消去電圧を用いて前記メモリセルのデータを消去する段階と、を含んでNAND型フラッシュメモリ素子のデータ消去方法を構成する。
【選択図】図1
Description
また、フラグビットに保存されたデータが"10"である場合、ステップ電圧を0.5Vにし、消去電圧が18.5Vになるまで消去電圧を0.5Vずつ増加させながら印加する(S300〜S306)(図4Bを参照)。
Claims (9)
- ドレイン及びソース選択トランジスタ及び多数のメモリセルからなるセルストリングが多数個配列されたメモリセルブロックを備えるフラッシュメモリ素子のデータ消去方法において、
消去しようとするブロックのメモリセルに第1消去電圧を印加する段階と、
第2検証電圧より高い第1検証電圧を用いて前記メモリセルの消去状態を検証する第1検証段階と、
前記第1検証段階をパスしていないメモリセルを第1グループに分類し、前記第1検証段階をパスしたメモリセルに対して第2検証電圧で検証する第2検証段階と、
前記第2検証電圧に対してパスしたメモリセルを第2グループに分類し、パスしていないメモリセルを第3グループに分類する段階と、
前記第1、第2及び第3グループのメモリセルに対して、それぞれ異なるステップ電圧及び消去電圧を用いて前記メモリセルのデータを消去する段階と、を含むことを特徴とするNAND型フラッシュメモリ素子のデータ消去方法。 - 前記第1消去電圧は、17Vであることを特徴とする請求項1に記載のNAND型フラッシュメモリ素子のデータ消去方法。
- 前記第1検証電圧は0.5Vで、前記第2検証電圧は0Vであることを特徴とする請求項1に記載のNAND型フラッシュメモリ素子のデータ消去方法。
- 前記第1グループのメモリセルに対して、ステップ電圧を1Vにし、消去電圧が19Vになるまで消去動作を行うことを特徴とする請求項1に記載のNAND型フラッシュメモリ素子のデータ消去方法。
- 前記第2グループのメモリセルに対して、ステップ電圧を0.5Vにし、消去電圧が18Vになるまで消去動作を行うことを特徴とする請求項1に記載のNAND型フラッシュメモリ素子のデータ消去方法。
- 前記第3グループのメモリセルに対して、ステップ電圧を0.5Vにし、消去電圧が18.5Vになるまで消去動作を行うことを特徴とする請求項1に記載のNAND型フラッシュメモリ素子のデータ消去方法。
- 前記メモリセルを第1〜第3グループに分類する段階で、
フラグセルに各グループに該当するデータを保存することを特徴とする請求項1に記載のNAND型フラッシュメモリ素子のデータ消去方法。 - 前記フラグセルは、2ビットで構成されることを特徴とする請求項7に記載のNAND型フラッシュメモリ素子のデータ消去方法。
- 前記ブロックに対して再び消去過程を繰り返すときは、前記フラグセルのデータを読み出した後、前記データに該当するグループの消去電圧及びステップ電圧を用いることを特徴とする請求項7に記載のNAND型フラッシュメモリ素子のデータ消去方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2006-0137139 | 2006-12-28 | ||
KR1020060137139A KR100811274B1 (ko) | 2006-12-28 | 2006-12-28 | 낸드형 플래쉬 메모리소자의 데이터 소거방법 |
Publications (2)
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JP2008165960A true JP2008165960A (ja) | 2008-07-17 |
JP5132268B2 JP5132268B2 (ja) | 2013-01-30 |
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JP2007293816A Expired - Fee Related JP5132268B2 (ja) | 2006-12-28 | 2007-11-13 | Nand型フラッシュメモリ素子のデータ消去方法 |
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US (1) | US7630255B2 (ja) |
JP (1) | JP5132268B2 (ja) |
KR (1) | KR100811274B1 (ja) |
CN (1) | CN101241761B (ja) |
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JP2012523646A (ja) * | 2009-04-09 | 2012-10-04 | サンディスク テクノロジーズ インコーポレイテッド | 不揮発性記憶装置のためのツーパス消去 |
US8335113B2 (en) | 2009-04-09 | 2012-12-18 | Renesas Electronics Corporation | Flash memory and data erasing method of the same |
US8553467B2 (en) | 2011-01-28 | 2013-10-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP2014059945A (ja) * | 2012-09-14 | 2014-04-03 | Freescale Semiconductor Inc | 適応的書き込み操作を用いる不揮発性メモリ(nvm) |
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2007
- 2007-06-29 US US11/770,872 patent/US7630255B2/en not_active Expired - Fee Related
- 2007-11-13 JP JP2007293816A patent/JP5132268B2/ja not_active Expired - Fee Related
- 2007-12-28 CN CN200710306930XA patent/CN101241761B/zh not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011526049A (ja) * | 2008-06-27 | 2011-09-29 | サンディスク コーポレイション | 最小限の追加時間ペナルティで障害を低減するために改良されたプログラミングアルゴリズム |
KR101546460B1 (ko) | 2008-06-27 | 2015-08-24 | 샌디스크 테크놀로지스, 인코포레이티드 | 최소 여분 시간 패널티를 갖는 혼란을 감소시키기 위한 개선된 프로그래밍 알고리즘 |
JP2012523646A (ja) * | 2009-04-09 | 2012-10-04 | サンディスク テクノロジーズ インコーポレイテッド | 不揮発性記憶装置のためのツーパス消去 |
US8335113B2 (en) | 2009-04-09 | 2012-12-18 | Renesas Electronics Corporation | Flash memory and data erasing method of the same |
US8553467B2 (en) | 2011-01-28 | 2013-10-08 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP2014059945A (ja) * | 2012-09-14 | 2014-04-03 | Freescale Semiconductor Inc | 適応的書き込み操作を用いる不揮発性メモリ(nvm) |
Also Published As
Publication number | Publication date |
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CN101241761A (zh) | 2008-08-13 |
JP5132268B2 (ja) | 2013-01-30 |
US20080158994A1 (en) | 2008-07-03 |
KR100811274B1 (ko) | 2008-03-07 |
CN101241761B (zh) | 2011-04-06 |
US7630255B2 (en) | 2009-12-08 |
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