JP2008130775A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2008130775A JP2008130775A JP2006313557A JP2006313557A JP2008130775A JP 2008130775 A JP2008130775 A JP 2008130775A JP 2006313557 A JP2006313557 A JP 2006313557A JP 2006313557 A JP2006313557 A JP 2006313557A JP 2008130775 A JP2008130775 A JP 2008130775A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 244
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 28
- 230000015556 catabolic process Effects 0.000 abstract description 32
- 239000000758 substrate Substances 0.000 abstract description 22
- 230000005684 electric field Effects 0.000 description 22
- 210000004027 cell Anatomy 0.000 description 21
- 230000004048 modification Effects 0.000 description 17
- 238000012986 modification Methods 0.000 description 17
- 230000000052 comparative effect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
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- 230000000779 depleting effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 210000003771 C cell Anatomy 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Abstract
【解決手段】セル部C及び終端部Sからなる半導体装置1において、半導体基板2、ドレイン電極3及びソース電極4を設ける。半導体基板2においては、ドレイン電極3に接続されたn型半導体層5と、スーパージャンクション構造をなすp型半導体ピラー層6及びn型半導体ピラー層7とを形成し、終端部Sにおける半導体基板2の上面に、p型ベース層8に接続されたp型リサーフ層13を形成する。そして、p型リサーフ層13に接続されるように、p型リサーフ層13上にn型リサーフ層14を形成する。これにより、リサーフ層を確実に空乏化させることができる。
【選択図】図1
Description
図1は、本発明の実施形態に係る半導体装置を例示する平面図及び断面図である。なお、図1の平面図においては、図を見易くするために半導体基板の構成のみを示し、半導体基板上の構成については図示を省略している。後述する図5及び図6においても同様である。
図2は、横軸にn型半導体ピラー層のドーズ量に対するp型半導体ピラー層のドーズ量の比の値をとり、縦軸に耐圧をとって、スーパージャンクション構造におけるドーズ量の比が半導体装置の耐圧に及ぼす影響を例示するグラフ図である。
なお、図2に示すドーズ量とは、X方向から見たときのp型半導体ピラー層6及びn型半導体ピラー層7のそれぞれの総ドーズ量であり、p型半導体ピラー層6のドーズ量をQp(cm−2)とし、n型半導体ピラー層7のドーズ量をQn(cm−2)とするとき、図2の横軸の値は、(Qp/Qn)と表すことができる。
また、図3は、本実施形態の比較例に係る半導体装置を例示する断面図、及びこの半導体装置の各部の電界強度をその位置に対応させて例示するグラフ図である。
図4(a)及び(b)は、半導体装置内の電位分布のシミュレーション結果を示す図であり、(a)は比較例を示し、(b)は本実施形態を示す。
先ず、本実施形態に係る半導体装置として、図1に示すn型リサーフ層が設けられた半導体装置1を想定する。また、比較例に係る半導体装置として、図3に示すn型リサーフ層が設けられていない半導体装置101を想定する。これらの半導体装置においては、Qp>Qnであるものとする。そして、これらの半導体装置に関して、ドレイン電極3に600Vの電位を印加し、ソース電極4に0Vの電位を印加した場合のポテンシャル分布をシミュレーションにより求める。この結果を図4(a)及び(b)に示す。
図5は、本変形例に係る半導体装置を例示する平面図及び断面図である。
図5に示すように、本変形例に係る半導体装置21においては、上方から見て、n型リサーフ層14がp型リサーフ層13よりも外側にずれている。これにより、n型リサーフ層14の外周部分を、p型リサーフ層13の直上域からはみ出させ、n型半導体ピラー層7に接続させることができる。本変形例における上記以外の構成及び作用効果は、前述の実施形態と同様である。
図6は、本変形例に係る半導体装置を例示する平面図及び断面図である。
図6に示すように、本変形例に係る半導体装置31においては、n型リサーフ層14が、複数本のストライプ状の部分に分割されており、各ストライプ状の部分が半導体装置31の中心から外縁に向かって延びるように、放射状に配列されている。すなわち、上方から見ると、p型リサーフ層13とn型リサーフ層14とが交互に配列されている。これにより、p型リサーフ層13とn型リサーフ層14との間のpn接合面の面積が増加し、リサーフ層全体をより容易に空乏化させることができる。
Claims (5)
- 電流を流すセル部及び前記セル部を囲む終端部からなる半導体装置において、
第1導電型の第1半導体層と、
前記第1半導体層に接続された第1の主電極と、
前記第1半導体層上に形成され、前記第1半導体層の上面に平行な方向に沿って交互に配列された第1導電型の第1半導体ピラー層及び第2導電型の第2半導体ピラー層からなるドリフト層と、
前記第2半導体ピラー層に接続されるように前記ドリフト層の表面に選択的に形成された第2導電型の半導体ベース層と、
前記半導体ベース層の表面に選択的に形成された第1導電型の半導体ソース層と、
前記ドリフト層の上方に設けられたゲート絶縁膜と、
前記ゲート絶縁膜により前記ドリフト層及び前記ベース層から絶縁されたゲート電極と、
前記半導体ベース層及び前記半導体ソース層に電気的に接続された第2の主電極と、
前記終端部における前記ドリフト層の表面に形成され、前記半導体ベース層に接続された第2導電型の第1半導体リサーフ層と、
前記第1半導体リサーフ層に接するように、前記第1半導体リサーフ層上に形成された第1導電型の第2半導体リサーフ層と、
を備えたことを特徴とする半導体装置。 - 相互に隣接する1対の前記第1半導体リサーフ層及び前記第2半導体リサーフ層において、前記第1半導体リサーフ層の不純物ドーズ量と前記第2半導体リサーフ層の不純物ドーズ量とが相互に略等しいことを特徴とする請求項1記載の半導体装置。
- 前記第1半導体リサーフ層及び前記第2半導体リサーフ層の外周側部分の不純物濃度は、前記第1半導体リサーフ層及び前記第2半導体リサーフ層の内周側部分の不純物濃度よりも低いことを特徴とする請求項1または2に記載の半導体装置。
- 前記第1半導体層の上面に垂直な方向から見て、前記第2半導体リサーフ層は前記第1半導体リサーフ層よりも前記半導体装置の外周側にずれていることを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。
- 前記第2半導体リサーフ層は複数本のストライプ状の部分に分割されており、前記第1半導体層の上面に垂直な方向から見て、前記ストライプ状の部分は前記半導体装置の中心から外縁に向かって延びるように、放射状に配列されていることを特徴とする請求項1〜4のいずれか1つに記載の半導体装置。
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JP2006313557A JP5196766B2 (ja) | 2006-11-20 | 2006-11-20 | 半導体装置 |
US11/936,412 US8227854B2 (en) | 2006-11-20 | 2007-11-07 | Semiconductor device having first and second resurf layers |
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JP2006313557A JP5196766B2 (ja) | 2006-11-20 | 2006-11-20 | 半導体装置 |
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JP2012243610A Division JP5655052B2 (ja) | 2012-11-05 | 2012-11-05 | 半導体装置 |
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JP2010123789A (ja) * | 2008-11-20 | 2010-06-03 | Toshiba Corp | 電力用半導体装置 |
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US8716789B2 (en) | 2012-03-23 | 2014-05-06 | Kabushiki Kaisha Toshiba | Power semiconductor device |
CN104992963A (zh) * | 2015-07-24 | 2015-10-21 | 杭州士兰微电子股份有限公司 | 超结结构的半导体器件及其制造方法、光刻版 |
US9577087B2 (en) | 2009-07-31 | 2017-02-21 | Fui Electric Co., Ltd. | Semiconductor apparatus |
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JP5198030B2 (ja) * | 2007-10-22 | 2013-05-15 | 株式会社東芝 | 半導体素子 |
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