JP2008124443A - 高電子移動度トランジスタ半導体デバイスおよびその製造方法 - Google Patents
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
【解決手段】半導体基板(100)上にフォトレジスト層(102)が堆積され、ウインド(106)がフォトレジスト層(102)内に電子ビーム・リソグラフィによって形成され、共形層(108)がフォトレジスト(102)上、およびウインド(106)内に堆積され、実質的に全ての共形層(108)がフォトレジスト層(102)およびウインドの底部から選択的に除去されて、ウインド(106)内に誘電体側壁(110)を形成する。
【選択図】 図1D
Description
PMMA層および共重合体層を分離する前に、等方性の反応性イオン・エッチングによりPMMA層の一部において誘電体層を部分的に除去することができる。誘電体層はSiNを含んでもよい。
Claims (20)
- 半導体基板上に半導体デバイスを形成する方法であって、
前記半導体基板上にフォトレジスト層を形成すること、
前記フォトレジスト層内にウインドを形成すること、
前記フォトレジスト層上、および前記ウインド内に誘電体材料からなる共形層を形成すること、
前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記ウインド内に誘電体側壁を形成すること、を備える方法。 - 前記ウインド内に金属膜を堆積すること、
前記ウインドを等方的にエッチングして、前記ウインドの前記誘電体側壁から前記共形層の一部を除去すること、
前記フォトレジスト層を分離し、前記金属膜から金属ゲートを形成すること、を備える請求項1に記載の方法。 - 前記フォトレジストの形成が、
前記半導体基板上にポリメチル・メタクリレート(PMMA)層を形成すること、
前記PMMA層上にポリメチル・メタクリレート−メタクリル酸(PMMA−MAA)共重合体層を形成することを含み、前記共形層の形成が前記PMMA層および前記PMMA−MAA共重合体層が流動しない温度で前記誘電体材料を堆積することを含む、請求項1または2に記載の方法。 - 前記共形層が窒化ケイ素(SiN)を含み、前記PMMA−MAA共重合体層の形成が前記フォトレジスト層の流動しない温度で前記フォトレジスト上に前記SiNを堆積することを含む、請求項3に記載の方法。
- 前記半導体基板がインジウム・リン(InP)基板からなる、請求項1乃至4のいずれか1項に記載の方法。
- 前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記誘電体側壁を形成することが、前記共形層に対し異方性誘導結合型プラズマ(ICP)エッチングを適用することを含む、請求項1乃至5のいずれか1項に記載の方法。
- 前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記誘電体側壁を形成することが、プラズマ・エネルギを制御するための10〜50Wの間の高周波(RF)バイアス電力、およびイオン生成を制御するための100〜500Wの間のRF ICP電力で前記共形層に対し異方性誘導結合型プラズマ(ICP)エッチングを適用することを含む、請求項1乃至5のいずれか1項に記載の方法。
- 前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記誘電体側壁を形成することが、前記フォトレジスト層および前記ウインドを方向性エッチングすることを含む、請求項1乃至5のいずれか1項に記載の方法。
- 前記ウインド内、および前記フォトレジスト上に金属膜を堆積すること、
前記フォトレジスト層を分離し、前記金属膜から金属T型ゲートを形成すること、を備える請求項1乃至8のいずれか1項に記載の方法。 - 前記金属膜が、チタン、白金および金の1つからなる、請求項9に記載の方法。
- 前記フォトレジスト層内に前記ウインドを形成することが、電子ビーム・リソグラフィ(EBL)によって前記ウインドを形成することを含む、請求項1乃至10のいずれか1項に記載の方法。
- III−V族半導体基板上に金属T型ゲートを形成する方法であって、ポリメチル・メタクリレート(PMMA)層が前記半導体基板上に堆積され、ポリメチル・メタクリレート−メタクリル酸(PMMA−MAA)共重合体層が前記PMMA層上に堆積され、ウインドが前記PMMA−MAA共重合体層および前記PMMA層内に形成されている、金属T型ゲートを形成する方法において、
前記PMMA−MAA共重合体層上、および前記ウインドを覆うように誘電体層を堆積すること、
前記誘電体層を選択的に除去して、前記ウインド内に誘電体側壁を残留させること、
蒸着により前記ウインド内に金属膜を堆積すること、
前記PMMA層および前記PMMA−MAA共重合体層を分離し、前記金属膜から金属T型ゲートを形成すること、を備える方法。 - 前記誘電体層を選択的に除去して、前記ウインド内に誘電体側壁を残留させることが、前記誘電体層に異方性誘導結合型プラズマ(ICP)エッチングを適用することを含む、請求項12に記載の方法。
- 前記PMMA層の一部において等方性の反応性イオン・エッチングによって前記誘電体層を部分的に除去した後、前記PMMA層および前記共重合体層を分離することを備える請求項12または13に記載の方法。
- 前記誘電体層が窒化シリコン(SiN)からなる、請求項12乃至14のいずれか1項に記載の方法。
- 300GHzから3THzの周波数で動作するサブ・ミリメータ波増幅器のための高電子移動度トランジスタ(HEMT)半導体デバイスであって、
III−V族基板と、
前記基板上に配置された第1ソース電極および第2ソース電極と、
前記基板上に配置されたドレイン電極と、
前記第1ソース電極と前記ドレイン電極の間に配置される第1金属ゲート・フィンガおよび前記ドレイン電極と前記第2ソース電極の間に配置される第2金属ゲート・フィンガであって、該第1および第2金属ゲート・フィンガの各々が約50nm未満で0nmより大きい幅を有する金属T型ゲートを備える、前記第1金属ゲート・フィンガおよび前記第2金属ゲート・フィンガとを備える、デバイス。 - 前記基板がIn0.75Ga0.25Asチャネルを有するインジウム・リン基板を含む、請求項16に記載の半導体デバイス。
- 前記第1および第2金属ゲート・フィンガの各々が、チタン、白金、および金の1つからなる前記金属T型ゲートを含む、請求項16または17に記載の半導体デバイス。
- 前記第1および第2金属ゲート・フィンガの各々が、約35nmの幅を有する前記金属T型ゲートを含む、請求項16乃至18のいずれか1項に記載の半導体デバイス。
- 前記第1および第2金属ゲート・フィンガの各々が、誘電体材料からなる側壁部分を有する前記金属T型ゲートを含む、請求項16乃至19のいずれか1項に記載の半導体デバイス。
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TWI455212B (zh) * | 2012-01-11 | 2014-10-01 | Univ Nat Chiao Tung | 形成一t型閘極結構的方法 |
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EP1923907A3 (en) | 2009-04-15 |
JP5525124B2 (ja) | 2014-06-18 |
US20090206369A1 (en) | 2009-08-20 |
JP2016157960A (ja) | 2016-09-01 |
JP6290283B2 (ja) | 2018-03-07 |
JP2014116638A (ja) | 2014-06-26 |
US7582518B2 (en) | 2009-09-01 |
JP6152352B2 (ja) | 2017-06-21 |
US7709860B2 (en) | 2010-05-04 |
US20080111157A1 (en) | 2008-05-15 |
EP1923907A2 (en) | 2008-05-21 |
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