TWI455212B - 形成一t型閘極結構的方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
- H01L21/28593—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T asymmetrical sectional shape
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Description
本發明是有關於一種閘極製程方法,且特別是有關於一種T型閘極製程方法。
具有極低雜訊比值的砷化鎵電晶體放大器乃是製造高性能的衛星接收器所必備。而極小線幅寬及低閘極阻值T型閘極乃是達到高增益及低雜訊所必備條件。在此種型閘極結構中,閘極上層較寬的部份乃是為了爭加橫截面面積及降低閘極電阻。而較窄的閘極根部乃是為了減少閘極電容。但因為閘極金屬蝕刻困難,因此常見之製程方法為利用電子束微影製程,於基板上製作一個已定型的T型開口,並回填閘極金屬形成T型閘電極。然而,此種製程相當緩慢。
因此,需要一種改良式的T型閘極形成方法。
有鑑於此,本發明的目的在提供一個T型閘極形成方法,以增進T型閘電極上下寬度比,彌補先前技術的缺點。
本發明之一態樣在提供一種形成T型閘極結構的方法。首先,提供一半導體基材,並於半導體基材上形成一具有至少兩種顯影速率之光阻體結構。接著,根據一遮罩,圖案化光阻體結構,其中係對該光阻體結構進行斜向曝光,並根據該至少兩種顯影速率顯影曝光後之光阻體結構,來形成一光阻槽道並暴露出部分半導體基材,其中所形成之光阻槽道具有一相較於底部還要寬的上方部分。接著,將閘極材質回填於光阻槽道,並移除圖案化光阻體結構,形成該T型閘極結構。
在一實施例中,以剝脫(lift-off)技術移除該圖案化光阻體結構。
在一實施例中,該光阻體結構之高度約為1um。
在一實施例中,對該光阻體結構進行斜向曝光更包括:對對該光阻體結構進行一第一斜向曝光;以及對該光阻體結構進行一第二斜向曝光,其中該第一斜向曝光和該第二斜向曝光之光線彼此交叉且交會於遮罩開口處。其中該第一斜向曝光以及該第二斜向曝光,係以相對於基板表面25度至60度之斜角對該光阻體結構進行曝光。
在一實施例中,於半導體基材上形成一光阻體結構更包括:形成一第一光阻層於該半導體基材上;形成一第二光阻層於該第一光阻層上;以及形成一第三光阻層於該第二光阻層上,其中該第一光阻層以及該第三光阻層與該第二光阻層相較,具有較低之顯影速率。
在一實施例中,第一光阻層以及第三光阻層為一聚甲基丙烯酸甲酯層(Polymethylmethacrylate,PMMA),而第二光阻層為一聚甲基異丙基酮層(POLY METHYL ISOPROPENYL KETONE,PMIPK)或是一聚合物層(Copolymer)。
綜合上述所言,本發明藉由斜向曝光,來增加第三光阻層與第二光阻層之曝光量,進而在顯影時,可使得第三光阻層與第二光阻層相對於第一光阻層有更大之溶解量。從而使得T型閘極結構之上層金屬層與下層金屬層具有明顯之寬度比,形成優良之T型閘極結構。
以下為本發明較佳具體實施例以所附圖示加以詳細說明,下列之說明及圖示使用相同之參考數字以表示相同或類似元件,並且在重複描述相同或類似元件時則予省略。
本發明是利用兩種具不同顯影速率的光阻,於基板上依序形成低顯影速率-高顯影速率-低顯影速率三層光阻體,並利用斜向曝光方法,使紫外光對準照射此三層光阻體,藉由不同之顯影速率,於顯影後,於基板上形成T型光阻槽道,在由蒸鍍法沉積閘極金屬後,移除光阻來形成T型閘電極結構。
第1圖至第6圖所示為根據本發明一較佳實施例之T型閘極結構形成方法。首先請參閱第1圖所示,於基板100上依序形成一第一光阻層101、一第二光阻層102以及一第三光阻層103之三層光阻體結構104,並於該三層光阻體結構104上沉積一金屬層,並利用光學微影及蝕刻製程,形成一具開口105a之圖案化金屬層105,開口105a用以定義出T型閘極於基板100上之位置。在一實施例中,開口105a之寬度約為2um,金屬層105為一鈦金屬層,而在其他之實施例中,亦可選擇鎳,金,鋁或銅,並利用濕式蝕刻圖案化鈦金屬層。此外,第一光阻層101以及第三光阻層103與第二光阻層102相較,具有較低之顯影速率。此第一光阻層101以及第三光阻層103為聚甲基丙烯酸甲酯層(Polymethylmethacrylate,PMMA),而第二光阻層102為聚甲基異丙基酮層(POLY METHYL ISOPROPENYL KETONE,PMIPK)或是一聚合物層(Copolymer)。因此,此三層光阻體結構104為PMMA/PMIPK/PMMA,或是PMMA/Copolymer/PMMA。在一實施例中,三層光阻體結構104之高度約為1um。
接著,請參閱第2圖所示,利用圖案化金屬層105作為罩幕,對三層光阻體結構104作光線110a與金屬層105非垂直之第一斜向曝光,以形成圖案並轉印於該三層光阻體結構104。此步驟之斜向角度係用以控制第二光阻層102相對於第一光阻層101在正x方向之內凹深度,以及第三光阻層103與基板100表面的傾角α1。在一實施例中,第一斜向曝光之角度與Y軸間之夾角為25~60度。
請參閱第3圖所示,利用圖案化金屬層105作為罩幕,對三層光阻體結構104作光線110b與金屬層105非垂直之第二斜向曝光形成圖案並轉印於該三層光阻體結構104。此步驟之斜向角度係用以控制第二光阻層102相對於第一光阻層101在負x方向之內凹深度,以及第三光阻層103與基板100表面的傾角α2。在一實施例中,第二斜向曝光之角度與Y軸間之夾角為25~60度。其中第一斜向曝光和第二斜向曝光之光線彼此交叉且交會於開口105a,第一斜向曝光和第二斜向曝光分別使用1/2曝光劑量。
接著,如第4圖所示,蝕刻移除金屬層105,在一實施例中,是以濕式蝕刻,例如稀釋氫氟酸(DHF)蝕刻移除金屬層105。並對三層光阻體結構104進行光阻顯影,在一實施例中,若此三層光阻體結構104為PMMA/PMIPK/PMMA,則一1:3甲基異丁基酮(MIBK)和異丙醇(IPA)的混合顯影液被用來對此三層光阻體結構104進行顯影,並暴露出基板100表面,而緊接著進行一個乾式或濕式的浸洗製程,此一浸洗製程較佳為使用傳統稀釋氯化氫,而形成如第4圖所示之T型光阻槽道107。其中所謂之T型光阻槽道107,具有對稱且往下逐漸縮小的T形外觀,於第一光阻層101中具有相對於基板100形成傾角α1和α2之兩傾斜側璧,共同構成此T型光阻槽道107之頸部。T型閘極結構之下層金屬層佈設於頸部中,而T型閘極結構之上層金屬層則是延著兩傾斜側壁延展而佈設於第一光阻層101上。其中,T型光阻槽道107之寬度由最上方開口107a往下先擴大再縮小至頸部之開口107b並暴露出基板100之表面。T型光阻槽道之最上方開口107a可決定閘極阻值,而T型光阻槽道107之頸部開口107b則用以決定閘極之有效長度。
接著,如第5圖所示,以蒸鍍法沉積閘極金屬106,填滿T型光阻槽道107。其中閘極金屬材質較佳為使用鎳/金,在其他實施例中,可以由其它材質所組成,例如金屬鉬、鎢、鈦、鉑以及鋡或是以上物質的混合物。最後,如第6圖所示,利用剝脫(lift-off)技術移除光阻體結構104,而形成本發明之T型閘極結構108,在一實施例中,T型閘極結構108為鎳/金雙層結構,其中鎳厚度約為200埃,而金厚度約為3000埃。
第7圖所示為根據本發明之方法完成之T型閘極結構電子顯微鏡影像。其中,此T型閘極結構具有0.6微米之閘極有效長度,以及傾角約為30度之兩傾斜側璧。
綜合上述所言,由於被曝光之光阻層會發生光分解反應,並被顯影液所溶解而從基板上移除。因此,本發明藉由斜向曝光,來增加第三光阻層與第二光阻層之曝光量,進而在顯影時,可使得第三光阻層與第二光阻層相對於第一光阻層有更大之溶解量。且藉由斜向曝光,可於第一光阻層中形成大傾角之兩傾斜側璧,從而使得T型閘極結構之上層金屬層與下層金屬層之間具有明顯之寬度比,形成優良之T型閘極結構。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...基板
101...第一光阻層
102...第二光阻層
103...第三光阻層
104...三層光阻體結構
105...圖案化金屬層
105a...開口
106...閘極金屬
107...T型光阻槽道
107a和107b...開口
108...T型閘極結構
110a和110b...光線
α1和α2...傾角
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:
第1圖至第6圖所示為根據本發明一較佳實施例之T型閘極結構形成方法。
第7圖所示為根據本發明之方法完成之T型閘極結構電子顯微鏡影像。
100...基板
101...第一光阻層
102...第二光阻層
103...第三光阻層
104...三層光阻體結構
105...圖案化金屬層
110a...光線
Claims (10)
- 一種形成一T型閘極結構的方法,至少包括以下步驟:提供一半導體基材;於該半導體基材上形成一光阻體結構,其中該光阻體結構具有至少兩種顯影速率;形成一遮罩於該光阻體結構上,其中該遮罩具有一開口;以該遮罩為罩幕,圖案化該光阻體結構,其中對該光阻體結構進行斜向曝光,以及根據該至少兩種顯影速率顯影該曝光後光阻體結構,形成一光阻槽道並暴露出部分半導體基材,其中該光阻槽道具有一相較於底部還要寬的上方部分;將閘極材質回填該光阻槽道;以及移除該圖案化光阻體結構,形成該T型閘極結構。
- 如請求項1所述之方法,其中係以剝脫(lift-off)技術移除該圖案化光阻體結構。
- 如請求項1所述之方法,其中該光阻體結構之高度約為1um。
- 如請求項1所述之方法,其中該開口寬度為2um。
- 如請求項1所述之方法,其中對該光阻體結構進行斜向曝光更包括:對該光阻體結構進行一第一斜向曝光;以及對該光阻體結構進行一第二斜向曝光,其中該第一斜向曝光和該第二斜向曝光之光線彼此交叉且交會於該開口處。
- 如請求項5所述之方法,其中該第一斜向曝光以及該第二斜向曝光,係以相對於基板表面25度至60度之斜角對該光阻體結構進行曝光。
- 如請求項1所述之方法,其中該遮罩為鈦,鎳,金,鋁或銅金屬。
- 如請求項1所述之方法,其中於該半導體基材上形成一光阻體結構更包括:形成一第一光阻層於該半導體基材上;形成一第二光阻層於該第一光阻層上;以及形成一第三光阻層於該第二光阻層上,其中該第一光阻層以及該第三光阻層與該第二光阻層相較,具有較低之顯影速率。
- 如請求項8所述之方法,其中該第一光阻層以及該第三光阻層為一聚甲基丙烯酸甲酯層(Polymethylmethacrylate,PMMA),而該第二光阻層為一聚甲基異丙基酮層(POLY METHYL ISOPROPENYL KETONE,PMIPK)或是一聚合物層(Copolymer)。
- 如請求項1所述之方法,其中該T型閘極結構為鎳/金雙層結構,其中該鎳厚度約為200埃,而該金厚度約為3000埃。
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US4587138A (en) * | 1984-11-09 | 1986-05-06 | Intel Corporation | MOS rear end processing |
US20020155665A1 (en) * | 2001-04-24 | 2002-10-24 | International Business Machines Corporation, | Formation of notched gate using a multi-layer stack |
US20090206369A1 (en) * | 2006-11-14 | 2009-08-20 | Northrop Grumman Space & Mission Systems Corp. | High electron mobility transistor semiconductor device and fabrication method thereof |
US20100184262A1 (en) * | 2007-12-20 | 2010-07-22 | Northrop Grumman Space And Mission Systems Corp. | High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof |
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US4963501A (en) * | 1989-09-25 | 1990-10-16 | Rockwell International Corporation | Method of fabricating semiconductor devices with sub-micron linewidths |
TW248610B (en) | 1994-10-15 | 1995-06-01 | Tzy-Horng Chen | Implementing method for submicron T-type gate of microwave transistor |
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US4587138A (en) * | 1984-11-09 | 1986-05-06 | Intel Corporation | MOS rear end processing |
US20020155665A1 (en) * | 2001-04-24 | 2002-10-24 | International Business Machines Corporation, | Formation of notched gate using a multi-layer stack |
US20090206369A1 (en) * | 2006-11-14 | 2009-08-20 | Northrop Grumman Space & Mission Systems Corp. | High electron mobility transistor semiconductor device and fabrication method thereof |
US20100184262A1 (en) * | 2007-12-20 | 2010-07-22 | Northrop Grumman Space And Mission Systems Corp. | High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof |
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