JP5525124B2 - 高電子移動度トランジスタ半導体デバイスおよびその製造方法 - Google Patents
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 238000009616 inductively coupled plasma Methods 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
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- 150000002500 ions Chemical class 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
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- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003466 anti-cipated effect Effects 0.000 description 2
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 238000001015 X-ray lithography Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 229920003145 methacrylic acid copolymer Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
PMMA層および共重合体層を分離する前に、等方性の反応性イオン・エッチングによりPMMA層の一部において誘電体層を部分的に除去することができる。誘電体層はSiNを含んでもよい。
Claims (13)
- 半導体基板上に半導体デバイスを形成する方法であって、
前記半導体基板上にフォトレジスト層を形成すること、
前記フォトレジスト層内にウインドを形成すること、
前記フォトレジスト層上、および前記ウインド内に誘電体材料からなる共形層を形成すること、
前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記ウインド内に複数の誘電体側壁を形成すること、
前記ウインド内に金属膜を堆積すること、
前記ウインドを等方的にエッチングして、前記ウインドの前記底部上の前記複数の誘電体側壁の各々の一部を除去すること、
前記フォトレジスト層を分離し、前記金属膜から金属ゲートを形成すること、を備える方法。 - 前記フォトレジストの形成が、
前記半導体基板上にポリメチル・メタクリレート(PMMA)層を形成すること、
前記PMMA層上にポリメチル・メタクリレート−メタクリル酸(PMMA−MAA)共重合体層を形成することを含み、前記共形層の形成が前記PMMA層および前記PMMA−MAA共重合体層が流動しない温度で前記誘電体材料を堆積することを含む、請求項1に記載の方法。 - 前記共形層が窒化ケイ素(SiN)を含み、前記PMMA−MAA共重合体層の形成が前記フォトレジスト層の流動しない温度で前記フォトレジスト上に前記SiNを堆積することを含む、請求項2に記載の方法。
- 前記半導体基板がインジウム・リン(InP)基板からなる、請求項1乃至3のいずれか1項に記載の方法。
- 前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記誘電体側壁を形成することが、前記共形層に対し異方性誘導結合型プラズ
マ(ICP)エッチングを適用することを含む、請求項1乃至4のいずれか1項に記載の方法。 - 前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記誘電体側壁を形成することが、プラズマ・エネルギを制御するための10〜50Wの間の高周波(RF)バイアス電力、およびイオン生成を制御するための100〜500Wの間のRF ICP電力で前記共形層に対し異方性誘導結合型プラズマ(ICP)エッチングを適用することを含む、請求項1乃至4のいずれか1項に記載の方法。
- 前記フォトレジスト層および前記ウインドの底部から実質的に全ての前記共形層を選択的に除去し、前記誘電体側壁を形成することが、前記フォトレジスト層および前記ウインドを方向性エッチングすることを含む、請求項1乃至4のいずれか1項に記載の方法。
- 前記ウインド内、および前記フォトレジスト上に金属膜を堆積すること、
前記フォトレジスト層を分離し、前記金属膜から金属T型ゲートを形成すること、を備える請求項1乃至7のいずれか1項に記載の方法。 - 前記金属膜が、チタン、白金および金の1つからなる、請求項8に記載の方法。
- 前記フォトレジスト層内に前記ウインドを形成することが、電子ビーム・リソグラフィ(EBL)によって前記ウインドを形成することを含む、請求項1乃至9のいずれか1項に記載の方法。
- III−V族半導体基板上に金属T型ゲートを形成する方法であって、ポリメチル・メタクリレート(PMMA)層が前記半導体基板上に堆積され、ポリメチル・メタクリレート−メタクリル酸(PMMA−MAA)共重合体層が前記PMMA層上に堆積され、ウインドが前記PMMA−MAA共重合体層および前記PMMA層内に形成されている、金属T型ゲートを形成する方法において、
前記PMMA−MAA共重合体層上、および前記ウインドを覆うように誘電体層を堆積すること、
前記誘電体層を選択的に除去して、前記ウインド内に複数の誘電体側壁を残留させること、
蒸着により前記ウインド内に金属膜を堆積すること、
等方性の反応性イオン・エッチングによって前記ウインドの底部上の前記複数の誘電体側壁の各々の一部を除去すること、
前記PMMA層および前記PMMA−MAA共重合体層を分離し、前記金属膜から金属T型ゲートを形成すること、を備える方法。 - 前記誘電体層を選択的に除去して、前記ウインド内に誘電体側壁を残留させることが、前記誘電体層に異方性誘導結合型プラズマ(ICP)エッチングを適用することを含む、請求項11に記載の方法。
- 前記誘電体層が窒化シリコン(SiN)からなる、請求項11または12に記載の方法。
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US11/598,817 US7582518B2 (en) | 2006-11-14 | 2006-11-14 | High electron mobility transistor semiconductor device and fabrication method thereof |
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US7558371B2 (en) * | 2007-10-18 | 2009-07-07 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Method of generating X-ray diffraction data for integral detection of twin defects in super-hetero-epitaxial materials |
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US9614026B2 (en) | 2013-03-13 | 2017-04-04 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices |
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-
2006
- 2006-11-14 US US11/598,817 patent/US7582518B2/en active Active
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2007
- 2007-09-18 EP EP07018243A patent/EP1923907A3/en not_active Withdrawn
- 2007-09-27 JP JP2007251161A patent/JP5525124B2/ja active Active
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2009
- 2009-04-29 US US12/432,113 patent/US7709860B2/en active Active
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JP6152352B2 (ja) | 2017-06-21 |
EP1923907A2 (en) | 2008-05-21 |
US20080111157A1 (en) | 2008-05-15 |
JP2014116638A (ja) | 2014-06-26 |
JP6290283B2 (ja) | 2018-03-07 |
JP2008124443A (ja) | 2008-05-29 |
US20090206369A1 (en) | 2009-08-20 |
US7709860B2 (en) | 2010-05-04 |
JP2016157960A (ja) | 2016-09-01 |
EP1923907A3 (en) | 2009-04-15 |
US7582518B2 (en) | 2009-09-01 |
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