JP2008097804A - 電圧制御装置および電圧制御方法 - Google Patents
電圧制御装置および電圧制御方法 Download PDFInfo
- Publication number
- JP2008097804A JP2008097804A JP2007214164A JP2007214164A JP2008097804A JP 2008097804 A JP2008097804 A JP 2008097804A JP 2007214164 A JP2007214164 A JP 2007214164A JP 2007214164 A JP2007214164 A JP 2007214164A JP 2008097804 A JP2008097804 A JP 2008097804A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- burn
- active
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 17
- 230000004044 response Effects 0.000 claims abstract description 87
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 42
- 230000001934 delay Effects 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
- 230000007704 transition Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060099652A KR100845774B1 (ko) | 2006-10-13 | 2006-10-13 | 반도체 메모리 장치 및 이를 이용한 전압 제어 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008097804A true JP2008097804A (ja) | 2008-04-24 |
| JP2008097804A5 JP2008097804A5 (enExample) | 2010-09-24 |
Family
ID=39302947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007214164A Pending JP2008097804A (ja) | 2006-10-13 | 2007-08-20 | 電圧制御装置および電圧制御方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7502268B2 (enExample) |
| JP (1) | JP2008097804A (enExample) |
| KR (1) | KR100845774B1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009268058A (ja) * | 2008-04-28 | 2009-11-12 | Hynix Semiconductor Inc | センシング遅延回路及びこれを用いた半導体メモリー装置 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100845776B1 (ko) * | 2006-11-23 | 2008-07-14 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 센스앰프 제어회로 및 방법 |
| KR101539402B1 (ko) * | 2008-10-23 | 2015-07-27 | 삼성전자주식회사 | 반도체 패키지 |
| KR101047003B1 (ko) * | 2009-06-26 | 2011-07-06 | 주식회사 하이닉스반도체 | 프리차지신호 생성회로 및 반도체 메모리 장치 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61265792A (ja) * | 1985-05-20 | 1986-11-25 | Fujitsu Ltd | 半導体記憶回路 |
| JPH01162296A (ja) * | 1987-12-19 | 1989-06-26 | Sony Corp | Ｄｒａｍ |
| JPH0855497A (ja) * | 1994-06-08 | 1996-02-27 | Samsung Electron Co Ltd | 半導体メモリ装置のバーンインテスト回路 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62228177A (ja) * | 1986-03-29 | 1987-10-07 | Toshiba Corp | 半導体集積回路用許容入力電圧検査回路 |
| US5402375A (en) * | 1987-11-24 | 1995-03-28 | Hitachi, Ltd | Voltage converter arrangement for a semiconductor memory |
| JP2737293B2 (ja) * | 1989-08-30 | 1998-04-08 | 日本電気株式会社 | Ｍｏｓ型半導体記憶装置 |
| JP2821278B2 (ja) * | 1991-04-15 | 1998-11-05 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路 |
| US5901105A (en) * | 1995-04-05 | 1999-05-04 | Ong; Adrian E | Dynamic random access memory having decoding circuitry for partial memory blocks |
| JP3607760B2 (ja) | 1995-10-13 | 2005-01-05 | 富士通株式会社 | 半導体集積回路装置 |
| JPH10106257A (ja) * | 1996-09-06 | 1998-04-24 | Texas Instr Inc <Ti> | 集積回路のメモリ装置及びプリチャージ動作を与える方法 |
| JP3742191B2 (ja) * | 1997-06-06 | 2006-02-01 | 株式会社東芝 | 半導体集積回路装置 |
| JP4090570B2 (ja) * | 1998-06-02 | 2008-05-28 | 株式会社ルネサステクノロジ | 半導体装置、データ処理システム及び不揮発性メモリセルの閾値変更方法 |
| KR100281693B1 (ko) * | 1998-09-02 | 2001-02-15 | 윤종용 | 고속 삼상 부스터 회로 |
| JP3863313B2 (ja) * | 1999-03-19 | 2006-12-27 | 富士通株式会社 | 半導体記憶装置 |
| JP4555416B2 (ja) * | 1999-09-22 | 2010-09-29 | 富士通セミコンダクター株式会社 | 半導体集積回路およびその制御方法 |
| US6563746B2 (en) * | 1999-11-09 | 2003-05-13 | Fujitsu Limited | Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode |
| KR100333710B1 (ko) * | 1999-12-28 | 2002-04-22 | 박종섭 | 안정적인 리드 동작을 위한 디디알 에스디램 |
| JP3856424B2 (ja) * | 2000-12-25 | 2006-12-13 | 株式会社東芝 | 半導体記憶装置 |
| JP2002231000A (ja) * | 2001-02-05 | 2002-08-16 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100505702B1 (ko) * | 2003-08-20 | 2005-08-02 | 삼성전자주식회사 | 웨이퍼 테스트와 포스트 패키지 테스트에서 선택적으로프로그램 가능한 반도체 메모리 장치의 리페어 장치 및 그리페어 방법 |
| KR100586555B1 (ko) * | 2005-01-17 | 2006-06-08 | 주식회사 하이닉스반도체 | 내부전압 생성 제어회로 및 이를 이용한 내부전압 생성회로 |
-
2006
- 2006-10-13 KR KR1020060099652A patent/KR100845774B1/ko not_active Expired - Fee Related
-
2007
- 2007-07-05 US US11/822,358 patent/US7502268B2/en active Active
- 2007-08-20 JP JP2007214164A patent/JP2008097804A/ja active Pending
-
2009
- 2009-02-03 US US12/364,670 patent/US7916566B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61265792A (ja) * | 1985-05-20 | 1986-11-25 | Fujitsu Ltd | 半導体記憶回路 |
| JPH01162296A (ja) * | 1987-12-19 | 1989-06-26 | Sony Corp | Ｄｒａｍ |
| JPH0855497A (ja) * | 1994-06-08 | 1996-02-27 | Samsung Electron Co Ltd | 半導体メモリ装置のバーンインテスト回路 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009268058A (ja) * | 2008-04-28 | 2009-11-12 | Hynix Semiconductor Inc | センシング遅延回路及びこれを用いた半導体メモリー装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20080033683A (ko) | 2008-04-17 |
| US7502268B2 (en) | 2009-03-10 |
| US20090141572A1 (en) | 2009-06-04 |
| US20080089148A1 (en) | 2008-04-17 |
| US7916566B2 (en) | 2011-03-29 |
| KR100845774B1 (ko) | 2008-07-14 |
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