JP2008091888A - 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 - Google Patents
基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 Download PDFInfo
- Publication number
- JP2008091888A JP2008091888A JP2007223389A JP2007223389A JP2008091888A JP 2008091888 A JP2008091888 A JP 2008091888A JP 2007223389 A JP2007223389 A JP 2007223389A JP 2007223389 A JP2007223389 A JP 2007223389A JP 2008091888 A JP2008091888 A JP 2008091888A
- Authority
- JP
- Japan
- Prior art keywords
- input
- chip
- bond pads
- output bond
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 115
- 238000000034 method Methods 0.000 title claims abstract description 102
- 238000004806 packaging method and process Methods 0.000 title claims description 25
- 239000000463 material Substances 0.000 claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 6
- 238000001125 extrusion Methods 0.000 claims description 2
- 238000001771 vacuum deposition Methods 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims 1
- 239000000289 melt material Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000004927 fusion Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 76
- 229910000679 solder Inorganic materials 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 14
- 230000008569 process Effects 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910020935 Sn-Sb Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 229910008757 Sn—Sb Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000000383 hazardous chemical Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1183—Reworking, e.g. shaping
- H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13017—Shape in side view being non uniform along the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Abstract
【解決手段】基板42にある各入出力ボンドパッド50上に、それぞれに対応するスタッドバンプ52を形成し、チップ40にある各入出力ボンドパッド46上に可融材料層48をを形成し、そのスタッドバンプ52上に、裏返しにしたチップ40の入出力ボンドパッド46を位置合わせして載せ加熱することにより、各スタッドバンプ52が、チップ40上のそれぞれに対応する入出力ボンドパッド46と融着されて、基板42にある各入出力ボンドパッド50がチップ40上のそれぞれに対応する入出力ボンドパッド46に電気的に接続される。
【選択図】図1
Description
さらに別の態様は、集積回路、ディスプレイ、メモリ素子などのマイクロデバイスを対象とする。そうしたマイクロデバイスの一実施形態は、少なくとも1つのマイクロ回路を画定し、複数の入出力ボンドパッドを備えるチップを備える。このマイクロデバイスは、チップの入出力ボンドパッドに対応する複数の入出力ボンドパッドを画定する基板も含む。基板の各入出力ボンドパッド上に、それぞれに対応するスタッドバンプがあり、各スタッドバンプは、チップ上のそれぞれに対応する入出力ボンドパッドに取り付けられる。「基板」は、例えば、チップ用パッケージのそれぞれの部分でも、耐久性のある実用的な基礎をチップにもたらし、チップへの入出力接続の形成を容易にする、チップが取り付けられるさまざまな構造のいずれかでもよい。
本方法は、ダイ上にはんだボールまたはバンプを形成する必要なく、ダイ上の入出力ボンドパッドと、基板、キャリア、リードフレームなど(それらは全て一般に、「基板」と呼ばれる)上の対応する入出力ボンドパッドとの間に、所望の相互接続を実現するものである。したがって、(a)実質的により微細な入出力接続のピッチが実現される、(b)入出力接続を、ダイの周辺領域内だけでなく、ダイの有効回路領域内を含めて、ダイの表面上の実質的にどこにでも形成し(「エリアアレイ相互接続」と呼ばれる)、それによって、周辺入出力接続で実現可能なよりも実質的に多くの入出力接続を設けることができる、また(c)鉛を使用する必要なしに、入出力相互接続を形成し、それによって、完成したデバイスの汚染の潜在源をなくすことができる。さらに、それぞれの部分が、ウェーハ製作環境、およびチップ組立て環境により適している(より「やさしい」、すなわち、より適合性がある)。これにより、「製作」ステップの、下流の「組立て」ステップからのより適切でより顕著な分離がもたらされ、ダイと基板の間に入出力相互接続を形成する従来の方法に比べて、ダイあたりの製作コストが低減される。
42 基板
44 アンダーバンプメタライゼーション、UBM、UBM領域
46 入出力ボンドパッド
48 可融層、可融材料
50 入出力ボンドパッド
52 スタッドバンプ
54 ワイヤ
55 面、接面、表面
56 ボールボンド、球
58 平坦な上面
60 領域
62 チップ下空間、ダイ下空間
64 スタッドバンプ
65 接続
66 接続
70 ダイ
72 基板
74 UBM
76 入出力ボンドパッド
78 可融層
80 入出力ボンドパッド
82 スタッドバンプ
85 ベース
Claims (37)
- チップ上の複数の入出力ボンドパッドを、基板上の対応する複数の入出力ボンドパッドに電気的に接続する方法であって、
前記基板上にある前記複数の入出力ボンドパッド上に、それぞれに対応するスタッドバンプを形成するステップと、
前記チップを裏返しにして、前記裏返しにされたチップを前記スタッドバンプ上に、前記チップ上の前記複数の入出力ボンドパッドが前記基板上の対応するスタッドバンプと位置合わせされるように載せるステップと、
前記チップ上の前記複数の入出力ボンドパッドを、前記それぞれに対応するスタッドバンプに、前記それぞれに対応するスタッドバンプを前記チップ上の前記複数の入出力ボンドパッドに電気的に接続するように取り付けるステップと
を含む方法。 - 前記チップ上の前記複数の入出力ボンドパッドを、前記それぞれに対応するスタッドバンプに取り付ける前記ステップの前に、前記チップ上にある前記複数の入出力ボンドパッドのそれぞれ上に、アンダーバンプメタライゼーション(UBM)を形成するステップをさらに含む、請求項1に記載の方法。
- 前記チップ上の前記複数の入出力ボンドパッドを、前記それぞれに対応するスタッドバンプに取り付ける前記ステップが、前記スタッドバンプを、前記複数の入出力ボンドパッドに融着させるステップを含む、請求項1に記載の方法。
- 前記スタッドバンプを、前記複数の入出力ボンドパッドに融着させる前記ステップが、
可融材料からなる前記スタッドバンプを形成するステップと、
前記スタッドバンプ上に、前記裏返しにされたチップを載せる前記ステップの後に、前記スタッドバンプの前記可融材料の少なくとも一部分を、前記複数の入出力ボンドパッドの対応するものへ流れさせて、前記スタッドバンプの前記可融材料の少なくとも一部分に、前記複数の入出力ボンドパッドの対応するものとの接続を形成させるステップと
を含む、請求項3に記載の方法。 - 前記スタッドバンプを、前記複数の入出力ボンドパッドに融着させる前記ステップが、
前記チップ上にある前記複数の入出力ボンドパッド上に、可融材料からなる層を形成するステップと、
前記スタッドバンプ上に、前記裏返しにされたチップを載せる前記ステップの後に、前記可融材料の一部分を、前記複数の入出力ボンドパッドそれぞれから前記それぞれに対応するスタッドバンプへ流れさせて、したがって、前記可融材料の一部分に、前記複数の入出力ボンドパッドと前記それぞれに対応するスタッドバンプとの間に接続を形成させるステップと
を含む、請求項3に記載の方法。 - 前記チップ上にある前記複数の入出力ボンドパッド上に、可融材料からなる前記層がその上に形成されるアンダーバンプメタライゼーション(UBM)を形成するステップをさらに含む、請求項5に記載の方法。
- 前記スタッドバンプが、ボンド・オン・トレースまたは押出しバンプ技法を使用して形成される、請求項1に記載の方法。
- チップ上の複数の入出力ボンドパッドを、基板上の対応する複数の入出力ボンドパッドに電気的に接続する方法であって、
前記チップ上にある前記複数の入出力ボンドパッドのそれぞれ上に、少なくとも1層のアンダーバンプメタライゼーション(UBM)を、前記チップ上の対応する各入出力ボンドパッドをUBM処理するように形成するステップと、
前記基板上にある各対応する入出力ボンドパッド上に、それぞれに対応するスタッドバンプを形成するステップと、
前記スタッドバンプ上に前記チップを、前記チップ上の前記複数の入出力ボンドパッドが、前記基板上の前記スタッドバンプの対応するものと位置合わせされるように載せるステップと、
前記チップ上の前記複数の入出力ボンドパッドを、前記基板上の前記それぞれに対応するスタッドバンプに、前記それぞれに対応するスタッドバンプを前記チップ上の前記複数の入出力ボンドパッドに電気的に接続するように接合するステップと
を含む方法。 - 少なくとも1層のUBMを形成する前記ステップが、それぞれの金属からなる複数の層を、前記複数の入出力ボンドパッドに施すステップを含む、請求項8に記載の方法。
- 前記少なくとも1層のUBMが、それぞれの金属を真空蒸着することによって形成される、請求項8に記載の方法。
- 前記チップ上の前記複数の入出力ボンドパッドを、前記それぞれに対応するスタッドバンプに接合する前記ステップが、前記スタッドバンプを、前記複数の入出力ボンドパッドに融着させるステップを含む、請求項8に記載の方法。
- 前記スタッドバンプを、前記複数の入出力ボンドパッドに融着させる前記ステップが、
可融材料からなる前記スタッドバンプを形成するステップと、
前記スタッドバンプ上に、前記チップを載せる前記ステップの後に、前記スタッドバンプの前記可融材料の少なくとも一部分を、前記複数の入出力ボンドパッドの対応するものへ流れさせて、前記スタッドバンプの前記可融材料の少なくとも一部分に、前記複数の入出力ボンドパッドの対応するものとの接続を形成させるステップと
を含む、請求項11に記載の方法。 - 前記スタッドバンプを、前記複数の入出力ボンドパッドに融着させる前記ステップが、
前記チップ上にあるUBM処理された入出力ボンドパッドそれぞれ上に、可融材料からなる層を形成するステップと、
前記スタッドバンプ上に、前記裏返しにされたチップを載せる前記ステップの後に、前記可融材料の一部分を、前記複数の入出力ボンドパッドそれぞれから前記それぞれに対応するスタッドバンプへ流れさせて、したがって、前記可融材料の一部分に、前記複数の入出力ボンドパッドと前記それぞれに対応するスタッドバンプとの間に接続を形成させるステップと
を含む、請求項11に記載の方法。 - 可融材料からなる前記層が、Snからなる層、またはSnの合金からなる層を備える、請求項13に記載の方法。
- 前記スタッドバンプが、
前記基板上の前記複数の入出力ボンドパッドに、それぞれに対応するワイヤをボールボンディングするステップと、
前記ワイヤを切断して、各ボールボンドのところにスタッドを形成するステップと
によって形成される、請求項13に記載の方法。 - 前記基板上に、ほぼ同一の高さの前記スタッドバンプを一括して形成するステップをさらに含む、請求項8に記載の方法。
- 前記スタッドバンプを形成する前記ステップの後かつ前記載せるステップの前に、前記チップを裏返しにするステップをさらに含む、請求項8に記載の方法。
- 前記チップと前記基板の間にアンダーフィルを施すステップをさらに含む、請求項8に記載の方法。
- 請求項1に記載の方法によって製造されるチップ。
- 請求項8に記載の方法によって製造されるチップ。
- 取付け面を有する基板と、
前記取付け面上に形成された複数の入出力ボンドパッドと、
前記取付け面上のそれぞれの入出力ボンドパッドに取り付けられた、それぞれに対応する第1の端部と、前記それぞれの入出力ボンドパッドから突き出す、それぞれに対応する第2の端部とを有する複数のスタッドバンプであって、前記第2の端部が、前記基板に取り付けられて前記基板上の前記複数の入出力ボンドパッドに電気的に接続されることが意図されるチップ上の対応するボンドパッドに対して可融な、複数のスタッドバンプと
を備える、チップパッケージング基板。 - 前記取付け面上の前記複数の入出力ボンドパッドが押し出される、請求項21に記載のチップパッケージング基板。
- 前記複数のスタッドバンプが、可融材料で形成される、請求項21に記載のチップパッケージング基板。
- 前記複数のスタッドバンプが、Au、Cu、あるいはそれらの金属の一方または両方の合金で形成される、請求項21に記載のチップパッケージング基板。
- 前記複数のスタッドバンプの前記第1の端部が、前記基板の前記複数の入出力ボンドパッドにボールボンディングされる、請求項24に記載のチップパッケージング基板。
- チップが、前記複数のスタッドバンプの前記第2の端部を前記チップの対応する入出力ボンドパッドに取り付けることによって取り付けられた、請求項21に記載のチップパッケージング基板。
- 少なくとも1つのマイクロ回路を画定し、複数の入出力ボンドパッドを備えるチップと、
前記チップの前記入出力ボンドパッドに対応する、複数の入出力ボンドパッドを画定する基板と、
前記基板の前記入出力ボンドパッドのそれぞれ上にある、それぞれに対応するスタッドバンプと、
各スタッドバンプを前記チップ上の前記入出力ボンドパッドそれぞれに接合する、可融材料からなるそれぞれのユニットと
を備えるマイクロデバイス。 - 前記スタッドバンプが、可融材料で形成され、
可融材料からなる前記ユニットが、前記スタッドバンプの前記可融材料の一部分である、
請求項27に記載のマイクロデバイス。 - 前記スタッドバンプが、前記基板の前記入出力ボンドパッドそれぞれに接合された第1の端部を有する非可融材料で形成され、可融材料からなるそれぞれのユニットによって、前記チップの前記入出力ボンドパッドの対応するものに接合される第2の端部を有する、請求項27に記載のマイクロデバイス。
- 前記基板が、前記チップ用パッケージのそれぞれの部分である、請求項27に記載のマイクロデバイス。
- 前記チップが、裏返しにされた構成である、請求項27に記載のマイクロデバイス。
- 可融材料からなる各ユニットと、前記チップ上の前記入出力ボンドパッドそれぞれとの間に、少なくとも1層のアンダーバンプメタライゼーションをさらに備える、請求項27に記載のマイクロデバイス。
- 前記チップと前記基板の間に、アンダーフィルをさらに備える、請求項27に記載のマイクロデバイス。
- 少なくとも1つのマイクロ回路および複数の入出力ボンドパッドを有するチップを、パッケージングする方法であって、
パッケージング基板上に、前記チップ上の前記入出力ボンドパッドに対応する複数の入出力ボンドパッドを形成するステップと、
前記パッケージング基板上にある各対応する入出力ボンドパッド上に、それぞれに対応するスタッドバンプを形成するステップと、
前記チップを裏返しにして、前記裏返しにされたチップを、前記チップ上の前記入出力ボンドパッドが、前記パッケージング基板上の前記スタッドバンプの対応するものと位置合わせされるように前記スタッドバンプ上に載せるステップと、
各スタッドバンプのところで、前記チップ上の前記入出力ボンドパッドそれぞれを前記それぞれに対応するスタッドバンプに、前記それぞれに対応するスタッドバンプを前記チップ上の前記入出力ボンドパッドそれぞれに電気的に接続するように、融着させるステップと
を含む方法。 - 前記チップ上にある各入出力ボンドパッド上に、可融材料からなる層を形成するステップと、
前記チップ上の前記入出力ボンドパッドそれぞれを前記それぞれに対応するスタッドバンプに、前記可融材料を前記スタッドバンプ上に流れさせ、したがって前記可融材料に、前記スタッドバンプと前記チップ上の前記入出力ボンドパッドとの間のそれぞれの電気的接続を完了させることによって融着させるステップと
をさらに含む、請求項34に記載の方法。 - 少なくとも1層のアンダーバンプメタライゼーションを、前記チップの前記入出力ボンドパッドに施すステップをさらに含む、請求項34に記載の方法。
- 請求項34に記載の方法によって製作された、パッケージング済みチップ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/525,493 | 2006-09-22 | ||
US11/525,493 US7713782B2 (en) | 2006-09-22 | 2006-09-22 | Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013144478A Division JP5624649B2 (ja) | 2006-09-22 | 2013-07-10 | 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008091888A true JP2008091888A (ja) | 2008-04-17 |
JP5435849B2 JP5435849B2 (ja) | 2014-03-05 |
Family
ID=39375657
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007223389A Active JP5435849B2 (ja) | 2006-09-22 | 2007-08-30 | 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 |
JP2013144478A Active JP5624649B2 (ja) | 2006-09-22 | 2013-07-10 | 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013144478A Active JP5624649B2 (ja) | 2006-09-22 | 2013-07-10 | 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 |
Country Status (4)
Country | Link |
---|---|
US (3) | US7713782B2 (ja) |
JP (2) | JP5435849B2 (ja) |
KR (1) | KR101380712B1 (ja) |
TW (1) | TWI431701B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017511603A (ja) * | 2014-03-28 | 2017-04-20 | インテル コーポレイション | Emibチップの相互接続 |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI245402B (en) * | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US9258904B2 (en) | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
US8193034B2 (en) | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US8174119B2 (en) * | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US7612444B2 (en) * | 2007-01-05 | 2009-11-03 | Stats Chippac, Inc. | Semiconductor package with flow controller |
US20090014852A1 (en) * | 2007-07-11 | 2009-01-15 | Hsin-Hui Lee | Flip-Chip Packaging with Stud Bumps |
JP2009049051A (ja) * | 2007-08-14 | 2009-03-05 | Elpida Memory Inc | 半導体基板の接合方法及びそれにより製造された積層体 |
US8043893B2 (en) | 2007-09-14 | 2011-10-25 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
US7868457B2 (en) * | 2007-09-14 | 2011-01-11 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
SG152101A1 (en) * | 2007-11-06 | 2009-05-29 | Agency Science Tech & Res | An interconnect structure and a method of fabricating the same |
US8039303B2 (en) | 2008-06-11 | 2011-10-18 | Stats Chippac, Ltd. | Method of forming stress relief layer between die and interconnect structure |
JP5176146B2 (ja) * | 2008-10-08 | 2013-04-03 | 富士通株式会社 | マイクロ可動素子および光スイッチング装置 |
JP5239722B2 (ja) | 2008-10-10 | 2013-07-17 | 富士通株式会社 | マイクロ可動素子および光スイッチング装置 |
US7915741B2 (en) * | 2009-02-24 | 2011-03-29 | Unisem Advanced Technologies Sdn. Bhd. | Solder bump UBM structure |
US8492197B2 (en) * | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
US20120267779A1 (en) * | 2011-04-25 | 2012-10-25 | Mediatek Inc. | Semiconductor package |
US8288871B1 (en) * | 2011-04-27 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduced-stress bump-on-trace (BOT) structures |
US9105552B2 (en) * | 2011-10-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9978656B2 (en) * | 2011-11-22 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming fine-pitch copper bump structures |
US10784221B2 (en) * | 2011-12-06 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of processing solder bump by vacuum annealing |
JP6107117B2 (ja) * | 2012-03-22 | 2017-04-05 | 豊田合成株式会社 | 固体装置及びその製造方法 |
KR101932727B1 (ko) * | 2012-05-07 | 2018-12-27 | 삼성전자주식회사 | 범프 구조물, 이를 갖는 반도체 패키지 및 이의 제조 방법 |
JP6154995B2 (ja) * | 2012-06-20 | 2017-06-28 | 新光電気工業株式会社 | 半導体装置及び配線基板、並びにそれらの製造方法 |
US9287204B2 (en) * | 2012-12-20 | 2016-03-15 | Stats Chippac, Ltd. | Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form |
US9806045B2 (en) * | 2013-08-29 | 2017-10-31 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface |
DE102015100521B4 (de) * | 2015-01-14 | 2020-10-08 | Infineon Technologies Ag | Halbleiterchip und Verfahren zum Bearbeiten eines Halbleiterchips |
US20160343646A1 (en) * | 2015-05-21 | 2016-11-24 | Qualcomm Incorporated | High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package |
KR101657003B1 (ko) * | 2015-06-09 | 2016-09-12 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스의 제조 방법 |
FR3041625B1 (fr) * | 2015-09-29 | 2021-07-30 | Tronics Microsystems | Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support |
CN108538726B (zh) * | 2017-03-03 | 2022-08-26 | Tdk株式会社 | 半导体芯片的制造方法 |
JP7251951B2 (ja) * | 2018-11-13 | 2023-04-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
TWI769022B (zh) * | 2021-07-22 | 2022-06-21 | 國立陽明交通大學 | 接合元件及其製備方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6437038A (en) * | 1987-07-31 | 1989-02-07 | Tanaka Electronics Ind | Junction of semiconductor materials |
JPH10135272A (ja) * | 1996-10-30 | 1998-05-22 | Matsushita Electric Works Ltd | フリップチップ実装方法 |
Family Cites Families (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04355933A (ja) | 1991-02-07 | 1992-12-09 | Nitto Denko Corp | フリツプチツプの実装構造 |
JPH04334035A (ja) * | 1991-05-10 | 1992-11-20 | Fujitsu Ltd | 半田ワイヤとそのワイヤを使用した半田バンプの形成方法 |
JP2678958B2 (ja) | 1992-03-02 | 1997-11-19 | カシオ計算機株式会社 | フィルム配線基板およびその製造方法 |
US5314651A (en) | 1992-05-29 | 1994-05-24 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
DE19524739A1 (de) * | 1994-11-17 | 1996-05-23 | Fraunhofer Ges Forschung | Kernmetall-Lothöcker für die Flip-Chip-Technik |
JP3353508B2 (ja) | 1994-12-20 | 2002-12-03 | ソニー株式会社 | プリント配線板とこれを用いた電子装置 |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
KR0182073B1 (ko) | 1995-12-22 | 1999-03-20 | 황인길 | 반도체 칩 스케일 반도체 패키지 및 그 제조방법 |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
JPH09260552A (ja) | 1996-03-22 | 1997-10-03 | Nec Corp | 半導体チップの実装構造 |
KR100216839B1 (ko) | 1996-04-01 | 1999-09-01 | 김규현 | Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조 |
JP3500032B2 (ja) | 1997-03-13 | 2004-02-23 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
JP3346263B2 (ja) | 1997-04-11 | 2002-11-18 | イビデン株式会社 | プリント配線板及びその製造方法 |
EP0993039B1 (en) | 1997-06-26 | 2006-08-30 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
JPH1126919A (ja) | 1997-06-30 | 1999-01-29 | Fuji Photo Film Co Ltd | プリント配線板 |
WO1999004430A1 (en) | 1997-07-21 | 1999-01-28 | Aguila Technologies, Inc. | Semiconductor flip-chip package and method for the fabrication thereof |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
US6335571B1 (en) | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
JP3421548B2 (ja) * | 1997-09-10 | 2003-06-30 | 富士通株式会社 | 半導体ベアチップ、半導体ベアチップの製造方法、及び半導体ベアチップの実装構造 |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
SG71734A1 (en) | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
JP3819576B2 (ja) | 1997-12-25 | 2006-09-13 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
JP2000031204A (ja) | 1998-07-07 | 2000-01-28 | Ricoh Co Ltd | 半導体パッケージの製造方法 |
US6246124B1 (en) * | 1998-09-16 | 2001-06-12 | International Business Machines Corporation | Encapsulated chip module and method of making same |
JP2000133672A (ja) | 1998-10-28 | 2000-05-12 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2000138261A (ja) * | 1998-11-02 | 2000-05-16 | Hitachi Ltd | 半導体装置の製造方法 |
JP3346320B2 (ja) | 1999-02-03 | 2002-11-18 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
JP2001068836A (ja) | 1999-08-27 | 2001-03-16 | Mitsubishi Electric Corp | プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法 |
JP2001102409A (ja) * | 1999-09-28 | 2001-04-13 | Matsushita Electronics Industry Corp | 半導体装置およびその製造方法 |
TW429492B (en) | 1999-10-21 | 2001-04-11 | Siliconware Precision Industries Co Ltd | Ball grid array package and its fabricating method |
US6774474B1 (en) | 1999-11-10 | 2004-08-10 | International Business Machines Corporation | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
US20030001286A1 (en) * | 2000-01-28 | 2003-01-02 | Ryoichi Kajiwara | Semiconductor package and flip chip bonding method therein |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6787918B1 (en) | 2000-06-02 | 2004-09-07 | Siliconware Precision Industries Co., Ltd. | Substrate structure of flip chip package |
US6717245B1 (en) | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
JP2002289768A (ja) * | 2000-07-17 | 2002-10-04 | Rohm Co Ltd | 半導体装置およびその製法 |
JP3554533B2 (ja) | 2000-10-13 | 2004-08-18 | シャープ株式会社 | チップオンフィルム用テープおよび半導体装置 |
US6815324B2 (en) * | 2001-02-15 | 2004-11-09 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US8158508B2 (en) | 2001-03-05 | 2012-04-17 | Megica Corporation | Structure and manufacturing method of a chip scale package |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
TW507341B (en) | 2001-11-01 | 2002-10-21 | Siliconware Precision Industries Co Ltd | Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate |
US6870276B1 (en) | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
TWI245402B (en) | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
TW536767B (en) * | 2002-03-01 | 2003-06-11 | Advanced Semiconductor Eng | Solder ball attaching process |
JP2003273145A (ja) | 2002-03-12 | 2003-09-26 | Sharp Corp | 半導体装置 |
US6780673B2 (en) | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
JP2004095923A (ja) | 2002-09-02 | 2004-03-25 | Murata Mfg Co Ltd | 実装基板およびこの実装基板を用いた電子デバイス |
TWI281718B (en) * | 2002-09-10 | 2007-05-21 | Advanced Semiconductor Eng | Bump and process thereof |
JP2004111676A (ja) | 2002-09-19 | 2004-04-08 | Toshiba Corp | 半導体装置、半導体パッケージ用部材、半導体装置の製造方法 |
US20050176233A1 (en) * | 2002-11-15 | 2005-08-11 | Rajeev Joshi | Wafer-level chip scale package and method for fabricating and using the same |
JP4114483B2 (ja) | 2003-01-10 | 2008-07-09 | セイコーエプソン株式会社 | 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器 |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
KR100529710B1 (ko) * | 2003-03-25 | 2005-11-23 | (주)케이나인 | 플립칩 패키징 방법 및 이를 이용한 발광다이오드의패키징 구조 |
US6774497B1 (en) | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
US20040232562A1 (en) | 2003-05-23 | 2004-11-25 | Texas Instruments Incorporated | System and method for increasing bump pad height |
US6849944B2 (en) | 2003-05-30 | 2005-02-01 | Texas Instruments Incorporated | Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad |
US6888255B2 (en) | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
TW572361U (en) | 2003-06-03 | 2004-01-11 | Via Tech Inc | Flip-chip package carrier |
TWI227556B (en) | 2003-07-15 | 2005-02-01 | Advanced Semiconductor Eng | Chip structure |
TWI241702B (en) | 2003-07-28 | 2005-10-11 | Siliconware Precision Industries Co Ltd | Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure |
KR100523330B1 (ko) | 2003-07-29 | 2005-10-24 | 삼성전자주식회사 | Smd 및 nsmd 복합형 솔더볼 랜드 구조를 가지는bga 반도체 패키지 |
TWI234258B (en) | 2003-08-01 | 2005-06-11 | Advanced Semiconductor Eng | Substrate with reinforced structure of contact pad |
TWI241675B (en) | 2003-08-18 | 2005-10-11 | Siliconware Precision Industries Co Ltd | Chip carrier for semiconductor chip |
KR100541394B1 (ko) | 2003-08-23 | 2006-01-10 | 삼성전자주식회사 | 비한정형 볼 그리드 어레이 패키지용 배선기판 및 그의제조 방법 |
US7271484B2 (en) | 2003-09-25 | 2007-09-18 | Infineon Technologies Ag | Substrate for producing a soldering connection |
JP2005109187A (ja) | 2003-09-30 | 2005-04-21 | Tdk Corp | フリップチップ実装回路基板およびその製造方法ならびに集積回路装置 |
US7462942B2 (en) | 2003-10-09 | 2008-12-09 | Advanpack Solutions Pte Ltd | Die pillar structures and a method of their formation |
US7294929B2 (en) | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
JP3851320B2 (ja) * | 2004-03-25 | 2006-11-29 | Tdk株式会社 | 回路装置及びその製造方法 |
WO2005093817A1 (ja) | 2004-03-29 | 2005-10-06 | Nec Corporation | 半導体装置及びその製造方法 |
TWI240389B (en) | 2004-05-06 | 2005-09-21 | Advanced Semiconductor Eng | High-density layout substrate for flip-chip package |
US7224073B2 (en) | 2004-05-18 | 2007-05-29 | Ultratera Corporation | Substrate for solder joint |
US7057284B2 (en) | 2004-08-12 | 2006-06-06 | Texas Instruments Incorporated | Fine pitch low-cost flip chip substrate |
JP2006108313A (ja) | 2004-10-04 | 2006-04-20 | Rohm Co Ltd | 実装基板および半導体装置 |
US20060131758A1 (en) | 2004-12-22 | 2006-06-22 | Stmicroelectronics, Inc. | Anchored non-solder mask defined ball pad |
CA2621505C (en) * | 2005-09-06 | 2015-06-30 | Aviv Soffer | 3-dimensional multi-layered modular computer architecture |
TWI298204B (en) | 2005-11-21 | 2008-06-21 | Advanced Semiconductor Eng | Structure of bumps forming on an under metallurgy layer and method for making the same |
JP4971769B2 (ja) | 2005-12-22 | 2012-07-11 | 新光電気工業株式会社 | フリップチップ実装構造及びフリップチップ実装構造の製造方法 |
US7317245B1 (en) | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US20080093749A1 (en) | 2006-10-20 | 2008-04-24 | Texas Instruments Incorporated | Partial Solder Mask Defined Pad Design |
-
2006
- 2006-09-22 US US11/525,493 patent/US7713782B2/en active Active
-
2007
- 2007-08-28 TW TW096131790A patent/TWI431701B/zh active
- 2007-08-30 JP JP2007223389A patent/JP5435849B2/ja active Active
- 2007-09-20 KR KR1020070095640A patent/KR101380712B1/ko active IP Right Grant
-
2010
- 2010-03-25 US US12/731,354 patent/US8193035B2/en active Active
- 2010-03-25 US US12/731,330 patent/US8525350B2/en active Active
-
2013
- 2013-07-10 JP JP2013144478A patent/JP5624649B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6437038A (en) * | 1987-07-31 | 1989-02-07 | Tanaka Electronics Ind | Junction of semiconductor materials |
JPH10135272A (ja) * | 1996-10-30 | 1998-05-22 | Matsushita Electric Works Ltd | フリップチップ実装方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017511603A (ja) * | 2014-03-28 | 2017-04-20 | インテル コーポレイション | Emibチップの相互接続 |
Also Published As
Publication number | Publication date |
---|---|
JP2013232676A (ja) | 2013-11-14 |
US20100178735A1 (en) | 2010-07-15 |
KR20080027161A (ko) | 2008-03-26 |
JP5624649B2 (ja) | 2014-11-12 |
US8193035B2 (en) | 2012-06-05 |
TW200830441A (en) | 2008-07-16 |
JP5435849B2 (ja) | 2014-03-05 |
US20080122117A1 (en) | 2008-05-29 |
US8525350B2 (en) | 2013-09-03 |
KR101380712B1 (ko) | 2014-04-04 |
US7713782B2 (en) | 2010-05-11 |
TWI431701B (zh) | 2014-03-21 |
US20100176510A1 (en) | 2010-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5624649B2 (ja) | 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法 | |
US6677674B2 (en) | Semiconductor package having two chips internally connected together with bump electrodes and both chips externally connected to a lead frame with bond wires | |
US6787903B2 (en) | Semiconductor device with under bump metallurgy and method for fabricating the same | |
US7420814B2 (en) | Package stack and manufacturing method thereof | |
TW201719837A (zh) | 半導體封裝以及製造其之方法 | |
KR20100128275A (ko) | 열 기계 플립 칩 다이 본딩 | |
KR20030019187A (ko) | 반도체 장치 및 그 제조 방법 | |
US20050151268A1 (en) | Wafer-level assembly method for chip-size devices having flipped chips | |
US6916687B2 (en) | Bump process for flip chip package | |
JP2003017531A (ja) | 半導体装置 | |
TWI223425B (en) | Method for mounting passive component on wafer | |
JP5420361B2 (ja) | 半導体装置の実装方法および半導体装置の製造方法 | |
CN113436977A (zh) | 在半导体器件和热交换器间产生热界面键合的装置和方法 | |
US6827252B2 (en) | Bump manufacturing method | |
US9601374B2 (en) | Semiconductor die assembly | |
JP2003068975A (ja) | 半導体装置およびその製造方法 | |
JP6593119B2 (ja) | 電極構造、接合方法及び半導体装置 | |
US20050133571A1 (en) | Flip-chip solder bump formation using a wirebonder apparatus | |
JP2004047537A (ja) | 半導体装置及びその製造方法 | |
WO2018198544A1 (ja) | 半導体装置の製造方法および半導体装置 | |
US11935824B2 (en) | Integrated circuit package module including a bonding system | |
JP4668608B2 (ja) | 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法 | |
JP3674550B2 (ja) | 半導体装置 | |
JPH09293748A (ja) | 半導体装置 | |
JP2002217232A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100507 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101006 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20110912 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120622 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120924 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121015 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130111 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130117 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130213 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20130312 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130710 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20130816 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131017 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131018 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131111 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131210 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5435849 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |