JP2008004612A - 超小型電力変換装置およびその製造方法 - Google Patents
超小型電力変換装置およびその製造方法 Download PDFInfo
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- JP2008004612A JP2008004612A JP2006170070A JP2006170070A JP2008004612A JP 2008004612 A JP2008004612 A JP 2008004612A JP 2006170070 A JP2006170070 A JP 2006170070A JP 2006170070 A JP2006170070 A JP 2006170070A JP 2008004612 A JP2008004612 A JP 2008004612A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 160
- 229910000859 α-Fe Inorganic materials 0.000 claims abstract description 76
- 239000004020 conductor Substances 0.000 claims abstract description 65
- 239000011347 resin Substances 0.000 claims abstract description 25
- 229920005989 resin Polymers 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000004907 flux Effects 0.000 abstract description 23
- 238000010586 diagram Methods 0.000 description 15
- 238000007747 plating Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 230000035699 permeability Effects 0.000 description 4
- 238000005488 sandblasting Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005536 corrosion prevention Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
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Abstract
【解決手段】コイル基板100の第2接続導体9がフェライト基板1の端部の側壁で下半分が露出し、第1外部電極7の外周部をフェライト基板1で囲こむことで、第2接続導体の外側を通る磁束を低減し、モールド樹脂14の密着性を高め、耐湿性の向上を図ることができる。
【選択図】 図1
Description
この発明の目的は、前記の課題を解決して、外部電極と第2接続導体の外側を通る磁束を減少させてノイズ低減を図り、さらに、モールド樹脂の密着性を損なわず、耐湿性に優れた超小型電力変換装置およびその製造方法を提供することにある。
前記コイル基板が、磁性絶縁基板と、該磁性絶縁基板の表裏面の中央部に形成されるコイル導体と、前記磁性絶縁基板の表裏面の周辺部に形成される外部電極とを有し、前記磁性絶縁基板の表裏面に形成される前記コイル導体が第1接続導体で接続されてコイルを構成し、前記磁性絶縁基板の表裏面に形成される前記外部電極が第2接続導体で接続され、該第2接続導体が前記磁性絶縁基板の表面側では該磁性絶縁基板で囲まれ、該磁性絶縁基板の裏面側では前記第2接続導体の側面が露出している構成とする。
また、前記前記コイル基板の表面側と前記電源ICチップの裏面側が絶縁性接着材で固着され、前記電源ICチップの表面に形成されたパッド電極と前記コイル基板の表面側に形成された外部電極がボンディングワイヤで電気的に接続するとよい。
また、前記前記コイル基板の表面側に形成された外部電極と前記電源ICチップの裏面側に形成されたパッド電極がスタッドバンプを介して固着するとよい。
磁性絶縁基板の表面側から内部に向かって複数の第1穴を形成し、該第1穴の周囲にスクライブラインとなる直線を挟んで互いに線対称となる位置に形成される2個の第2穴を1組として前記直線に沿って複数組の前記第2穴を形成する工程と、
前記磁性絶縁基板の裏面側の前記第1穴を投影した位置から内部に向かって前記第1穴と接続する第3穴を形成し、該第3穴の周囲の前記1組2個の第2穴を投影した位置を含み前記1組2個の第2穴と接続する細長の第4穴を形成する工程と、
異なる前記第1穴間、および異なる前記第2穴を結び前記磁性絶縁基板の表裏面にコイル導体を形成し、前記表裏面に形成されたコイル導体を接続する第1接続導体を前記第1穴および第3穴の側壁に形成し、前記磁性絶縁基板の表面側に前記第2穴を含み前記磁性絶縁基板で囲まれ2個1組の表面側の外部電極を前記スクライブラインとなる箇所から離し、該スクライブラインと線対称となる位置に該スクライブラインに沿って複数組形成し、前記裏面側に前記1組2個の第2穴を投影した位置の少なくとも一部を含む裏面側の外部電極を形成し、前記表裏面にそれぞれ形成されたそれぞれの外部電極と接続する第2接続導体を前記第2穴および第4穴の側壁に形成する工程と、
前記磁性絶縁基板の表面側に前記電源ICチップを接続する工程と、
前記磁性絶縁基板の表面側と前記電源ICチップの表面側を前記樹脂で被覆する工程と、
前記の組を構成する表面側の2個の外部電極に挟まれた箇所の前記スクライブラインに沿って前記磁性絶縁基板と前記樹脂を切断する工程とを含む製造方法とする。
このように、第1外部電極7はフェライト基板1の内側に形成され、フェライト基板1の全外周部でフェライト基板1の表面とモールド樹脂14が直接接着している。そのため、フェライト基板1の外周部でモールド樹脂14との密着性が低下することがなく、耐湿性の低下を防止できる。
図3に示すように、フェライト基板1の上半分では、第1外部電極7の外側を通る磁束21と内側を通る磁束22がある。一方、図4で示すように、フェライト基板1の下半分では、第2外部電極8の外側は第2接続導体9とスリット部23で遮断されて磁束21はなくなり、内側を通る磁束22のみとなる。そのため、第1外部電極7の外側を通る磁束21は、従来のコイル基板200において第1外部電極57の外側を通る磁束66に対して、おおよそ半分に低減する。その結果、第1外部電極7と第2外部電極8の間(第2接続導体9の両端)に発生する誘起電圧(ノイズ)が小さくなる。
この図はコイルに50mA流し、周波数2。5MHzでスイッチングさせたときの表面の第1外部電極7と裏面の第2外部電極8の間に発生した誘起電圧である。横軸は外部電極の位置記号で縦軸は誘起電圧である。参考までに従来のコイル基板200の場合も示した。従来のコイル基板200に対して本発明のコイル基板100は従来のコイル基板200に対して誘起電圧が半分程度に低くなっており、ノイズを半減させることができる。
また、この実施例では第1、第2外部電極7、8をフェライト基板1の外周部の四方に配置したが、X軸方向の外周部(2列)に配置してもよい。
先ず、図7(a)に示す外形が100mm□で板厚が525μmのフェライト基板1に外部電極及びコイル形成用のスルーホールを形成するために、図示しないフォトレジストを用いてフェライト基板1の表面と裏面にフォトリソグラフィを行い図7(b)のようなパターニングする。この際のフォトレジストはサンドブラストに耐える強度が必要な為、100μm厚のドライフィルムを用いる。続いて、図7(b)、(c)に示すようにサンドブラストでフェライト基板1の表面から周囲がフェライト基板1で囲まれ、第1接続導体6を形成するための複数の第1穴32と、この第1穴32群で囲まれた領域33の外側に1対の第2穴34を1組として複数組の第2穴34をフェライト基板1の厚さの半分以上の深さに掘る。この対となる第2穴34は、点線で示すスクライブライン31を挟んで線対称に配置する。尚、図7(a)はフェライト基板1の全体の平面図、図7(b)は図7(a)のB部拡大図で点線のスクライブライン31で囲まれた領域がコイル基板100となる箇所を示す平面図、図7(c)は図7(b)のX−X線で切断した要部断面図である。
つぎに、組を形成する一対の第2穴34間で第1外部電極7が形成されていない中間線に位置する図15の点線で示したスクライブライン31(切断線)に沿ってモールド樹脂14とフェライト基板1を切断する。その結果、図16(図1、図2と同じ)に示すようなフェライト基板1の表側では周辺部がフェライト基板1となり、フェライト基板1の裏側ではその側面に第2接続導体9が露出し、電源ICチップ10が搭載されたコイル基板100が形成される。この電源ICチップ10が搭載されたコイル基板100に図示しないコンデンサなどを固着して超小型電力変換装置が形成される。
2 第1スルーホール
3 第2スルーホール
4 第1コイル導体
5 第2コイル導体
6 第1接続導体
7 第1外部電極
8 第2外部電極
9 第2接続導体
10、10a 電源ICチップ
11、24 パッド電極
12 接着材
13 ボンディングワイヤ
14 モールド樹脂
21、22 磁束
23 スリット部
25 スタッドバンプ
31 スクライブライン
32 第1穴
33 領域
34 第2穴
35 第3穴
36 第4穴
37 メッキシード層
100 コイル導体
Claims (6)
- コイルと外部電極を有するコイル基板と、該コイル基板の表面側に固着する電源ICチップと、前記コイル基板の表面側と前記電源ICチップの表面側を被覆する樹脂とを有する超小型電力変換装置において、
前記コイル基板が、磁性絶縁基板と、該磁性絶縁基板の表裏面の中央部に形成されるコイル導体と、前記磁性絶縁基板の表裏面の周辺部に形成される外部電極とを有し、前記磁性絶縁基板の表裏面に形成される前記コイル導体が第1接続導体で接続されてコイルを構成し、前記磁性絶縁基板の表裏面に形成される前記外部電極が第2接続導体で接続され、該第2接続導体が前記磁性絶縁基板の表面側では該磁性絶縁基板で囲まれ、該磁性絶縁基板の裏面側では前記第2接続導体の側面が露出していることを特徴とする超小型電力変換装置。 - 前記磁性絶縁基板がフェライト基板であることを特徴とする請求項1に記載の超小型電力変換装置。
- 前記前記コイル基板の表面側と前記電源ICチップの裏面側が絶縁性接着材で固着され、前記電源ICチップの表面に形成されたパッド電極と前記コイル基板の表面側に形成された外部電極がボンディングワイヤで電気的に接続することを特徴とする請求項1または2に記載の超小型電力変換装置。
- 前記前記コイル基板の表面側に形成された外部電極と前記電源ICチップの裏面側に形成されたパッド電極がスタッドバンプを介して固着することを特徴とする請求項1または2に記載の超小型電力変換装置。
- コイル基板と、該コイル基板の表面側に固着する電源ICチップと、前記コイル基板の表面側と前記電源ICチップの表面側を被覆する樹脂とを有する超小型電力変換装置の製造方法において、
磁性絶縁基板の表面側から内部に向かって複数の第1穴を形成し、該第1穴の周囲にスクライブラインとなる直線を挟んで互いに線対称となる位置に形成される2個の第2穴を1組として前記直線に沿って複数組の前記第2穴を形成する工程と、
前記磁性絶縁基板の裏面側の前記第1穴を投影した位置から内部に向かって前記第1穴と接続する第3穴を形成し、該第3穴の周囲の前記1組2個の第2穴を投影した位置を含み前記1組2個の第2穴と接続する細長の第4穴を形成する工程と、
異なる前記第1穴間、および異なる前記第2穴を結び前記磁性絶縁基板の表裏面にコイル導体を形成し、前記表裏面に形成されたコイル導体を接続する第1接続導体を前記第1穴および第3穴の側壁に形成し、前記磁性絶縁基板の表面側に前記第2穴を含み前記磁性絶縁基板で囲まれ2個1組の表面側の外部電極を前記スクライブラインとなる箇所から離し、該スクライブラインと線対称となる位置に該スクライブラインに沿って複数組形成し、前記裏面側に前記1組2個の第2穴を投影した位置の少なくとも一部を含む裏面側の外部電極を形成し、前記表裏面にそれぞれ形成されたそれぞれの外部電極と接続する第2接続導体を前記第2穴および第4穴の側壁に形成する工程と、
前記磁性絶縁基板の表面側に前記電源ICチップを接続する工程と、
前記磁性絶縁基板の表面側と前記電源ICチップの表面側を前記樹脂で被覆する工程と、
前記の組を構成する表面側の2個の外部電極に挟まれた箇所の前記スクライブラインに沿って前記磁性絶縁基板と前記樹脂を切断する工程とを含むことを特徴とする超小型電力変換装置の製造方法。 - 前記外部電極が、シード層としてチタン膜と該チタン膜上に銅膜を形成し、もしくは銅膜のみを形成し、該シード層上に前記銅膜より厚い銅膜を形成して製作されることを特徴とする請求項5に記載の超小型電力変換装置の製造方法。
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