JP2007536771A5 - - Google Patents
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- Publication number
- JP2007536771A5 JP2007536771A5 JP2006554101A JP2006554101A JP2007536771A5 JP 2007536771 A5 JP2007536771 A5 JP 2007536771A5 JP 2006554101 A JP2006554101 A JP 2006554101A JP 2006554101 A JP2006554101 A JP 2006554101A JP 2007536771 A5 JP2007536771 A5 JP 2007536771A5
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power
- supply terminal
- transistor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 210000004027 cell Anatomy 0.000 claims 16
- 210000000352 storage cell Anatomy 0.000 claims 8
- 238000007726 management method Methods 0.000 claims 7
- 238000000034 method Methods 0.000 claims 5
- 230000014759 maintenance of location Effects 0.000 claims 3
- 230000003044 adaptive effect Effects 0.000 claims 2
- 238000005457 optimization Methods 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US54657404P | 2004-02-19 | 2004-02-19 | |
| PCT/US2005/001938 WO2005081758A2 (en) | 2004-02-19 | 2005-01-20 | Low leakage and data retention circuitry |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011217253A Division JP2012039644A (ja) | 2004-02-19 | 2011-09-30 | 低漏出のデータ保持回路を有する集積回路およびその方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007536771A JP2007536771A (ja) | 2007-12-13 |
| JP2007536771A5 true JP2007536771A5 (enExample) | 2009-09-24 |
Family
ID=34910791
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006554101A Withdrawn JP2007536771A (ja) | 2004-02-19 | 2005-01-20 | 低漏出のデータ保持回路 |
| JP2011217253A Withdrawn JP2012039644A (ja) | 2004-02-19 | 2011-09-30 | 低漏出のデータ保持回路を有する集積回路およびその方法 |
| JP2013095072A Expired - Lifetime JP5671577B2 (ja) | 2004-02-19 | 2013-04-30 | 低漏出のデータ保持回路を有する集積回路およびその方法 |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011217253A Withdrawn JP2012039644A (ja) | 2004-02-19 | 2011-09-30 | 低漏出のデータ保持回路を有する集積回路およびその方法 |
| JP2013095072A Expired - Lifetime JP5671577B2 (ja) | 2004-02-19 | 2013-04-30 | 低漏出のデータ保持回路を有する集積回路およびその方法 |
Country Status (6)
| Country | Link |
|---|---|
| EP (3) | EP1743422B1 (enExample) |
| JP (3) | JP2007536771A (enExample) |
| KR (2) | KR100999213B1 (enExample) |
| CN (2) | CN102055439B (enExample) |
| CA (2) | CA2595375A1 (enExample) |
| WO (1) | WO2005081758A2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010282411A (ja) * | 2009-06-04 | 2010-12-16 | Renesas Electronics Corp | 半導体集積回路、半導体集積回路の内部状態退避回復方法 |
| US8004922B2 (en) * | 2009-06-05 | 2011-08-23 | Nxp B.V. | Power island with independent power characteristics for memory and logic |
| JP5886127B2 (ja) * | 2011-05-13 | 2016-03-16 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US8824215B2 (en) * | 2011-09-12 | 2014-09-02 | Arm Limited | Data storage circuit that retains state during precharge |
| EP2982040A4 (en) | 2013-04-02 | 2017-03-29 | Hewlett-Packard Enterprise Development LP | State-retaining logic cell |
| CN104517645B (zh) * | 2014-05-16 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | 闪存低速读模式控制电路 |
| KR101470858B1 (ko) * | 2014-07-23 | 2014-12-09 | 주식회사 한국화이어텍 | 유무기 복합 하이브리드 수지 및 이를 이용한 코팅재 조성물 |
| CN104639104B (zh) * | 2015-02-06 | 2017-03-22 | 中国人民解放军国防科学技术大学 | 功能模块级多阈值低功耗控制装置及方法 |
| US11599185B2 (en) | 2015-07-22 | 2023-03-07 | Synopsys, Inc. | Internet of things (IoT) power and performance management technique and circuit methodology |
| US9859893B1 (en) * | 2016-06-30 | 2018-01-02 | Qualcomm Incorporated | High speed voltage level shifter |
| CN108347241B (zh) * | 2018-01-31 | 2021-09-07 | 京微齐力(北京)科技有限公司 | 一种低功耗多路选择器的结构 |
| CN108447514A (zh) * | 2018-04-02 | 2018-08-24 | 睿力集成电路有限公司 | 半导体存储器、休眠定态逻辑电路及其休眠定态方法 |
| TWI674754B (zh) * | 2018-12-28 | 2019-10-11 | 新唐科技股份有限公司 | 資料保持電路 |
| CN111049513B (zh) * | 2019-11-29 | 2023-08-08 | 北京时代民芯科技有限公司 | 一种带冷备份功能的轨到轨总线保持电路 |
| CN112859991B (zh) * | 2021-04-23 | 2021-07-30 | 深圳市拓尔微电子有限责任公司 | 电压处理电路和控制电压处理电路的方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07105174A (ja) * | 1993-10-07 | 1995-04-21 | Hitachi Ltd | 1チップマイクロコンピュータ |
| JPH09261013A (ja) * | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | Dフリップフロップ回路 |
| JPH10261946A (ja) * | 1997-03-19 | 1998-09-29 | Mitsubishi Electric Corp | 半導体集積回路 |
| JPH11214962A (ja) * | 1997-11-19 | 1999-08-06 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| KR100321976B1 (ko) * | 1997-12-29 | 2002-05-13 | 윤종용 | 인텔프로세서를위한오류허용전압조절모듈회로 |
| DE19811353C1 (de) * | 1998-03-16 | 1999-07-22 | Siemens Ag | Schaltungsanordnung zur Reduzierung des Leckstromes |
| JP2000013215A (ja) * | 1998-04-20 | 2000-01-14 | Nec Corp | 半導体集積回路 |
| JP3499748B2 (ja) * | 1998-06-12 | 2004-02-23 | Necエレクトロニクス株式会社 | 順序回路 |
| JP3341681B2 (ja) * | 1998-06-12 | 2002-11-05 | 日本電気株式会社 | 半導体集積論理回路 |
| US20020000872A1 (en) * | 1998-09-11 | 2002-01-03 | Yibin Ye | Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode |
| JP2000332598A (ja) * | 1999-05-17 | 2000-11-30 | Mitsubishi Electric Corp | ランダムロジック回路 |
| KR20010080575A (ko) * | 1999-09-28 | 2001-08-22 | 롤페스 요하네스 게라투스 알베르투스 | 액티브 모드와 슬립 모드에서 동작 가능한 전자 디지털 회로 |
| JP2001284530A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
| US6522171B2 (en) * | 2001-01-11 | 2003-02-18 | International Business Machines Corporation | Method of reducing sub-threshold leakage in circuits during standby mode |
| JP2003110022A (ja) * | 2001-09-28 | 2003-04-11 | Mitsubishi Electric Corp | 半導体集積回路 |
| US6538471B1 (en) * | 2001-10-10 | 2003-03-25 | International Business Machines Corporation | Multi-threshold flip-flop circuit having an outside feedback |
| EP1331736A1 (en) * | 2002-01-29 | 2003-07-30 | Texas Instruments France | Flip-flop with reduced leakage current |
| US6998895B2 (en) * | 2002-10-29 | 2006-02-14 | Qualcomm, Incorporated | System for reducing leakage in integrated circuits during sleep mode |
-
2005
- 2005-01-20 WO PCT/US2005/001938 patent/WO2005081758A2/en not_active Ceased
- 2005-01-20 EP EP05711776.4A patent/EP1743422B1/en not_active Expired - Lifetime
- 2005-01-20 KR KR1020107004248A patent/KR100999213B1/ko not_active Expired - Lifetime
- 2005-01-20 CN CN201010558923.0A patent/CN102055439B/zh not_active Expired - Lifetime
- 2005-01-20 CA CA002595375A patent/CA2595375A1/en not_active Abandoned
- 2005-01-20 CN CN2005800054871A patent/CN1969457B/zh not_active Expired - Lifetime
- 2005-01-20 KR KR1020067016624A patent/KR100984406B1/ko not_active Expired - Lifetime
- 2005-01-20 CA CA2738882A patent/CA2738882C/en not_active Expired - Lifetime
- 2005-01-20 EP EP19170964.1A patent/EP3537607B1/en not_active Expired - Lifetime
- 2005-01-20 EP EP11177203.4A patent/EP2387156A3/en not_active Ceased
- 2005-01-20 JP JP2006554101A patent/JP2007536771A/ja not_active Withdrawn
-
2011
- 2011-09-30 JP JP2011217253A patent/JP2012039644A/ja not_active Withdrawn
-
2013
- 2013-04-30 JP JP2013095072A patent/JP5671577B2/ja not_active Expired - Lifetime
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