CN1969457B - 低漏电及数据保持电路 - Google Patents
低漏电及数据保持电路 Download PDFInfo
- Publication number
- CN1969457B CN1969457B CN2005800054871A CN200580005487A CN1969457B CN 1969457 B CN1969457 B CN 1969457B CN 2005800054871 A CN2005800054871 A CN 2005800054871A CN 200580005487 A CN200580005487 A CN 200580005487A CN 1969457 B CN1969457 B CN 1969457B
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- CN
- China
- Prior art keywords
- circuit
- transistor
- sleep
- signal
- electric leakage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
IN | INB | OUT |
0 | 0 | 保持最后状态 |
0 | 1 | 0 |
1 | 0 | 1 |
1 | 1 | 无效 |
SLEEPB | IN | INB | OUT |
1 | 0 | 0 | 保持状态(数据保持) |
1 | 0 | 1 | 0 |
1 | 1 | 0 | 1 |
1 | 1 | 1 | 无效 |
0 | X | X | 保持状态 |
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US54657404P | 2004-02-19 | 2004-02-19 | |
US60/546,574 | 2004-02-19 | ||
PCT/US2005/001938 WO2005081758A2 (en) | 2004-02-19 | 2005-01-20 | Low leakage and data retention circuitry |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010558923.0A Division CN102055439B (zh) | 2004-02-19 | 2005-01-20 | 低漏电及数据保持电路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1969457A CN1969457A (zh) | 2007-05-23 |
CN1969457B true CN1969457B (zh) | 2010-12-29 |
Family
ID=34910791
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010558923.0A Active CN102055439B (zh) | 2004-02-19 | 2005-01-20 | 低漏电及数据保持电路 |
CN2005800054871A Active CN1969457B (zh) | 2004-02-19 | 2005-01-20 | 低漏电及数据保持电路 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010558923.0A Active CN102055439B (zh) | 2004-02-19 | 2005-01-20 | 低漏电及数据保持电路 |
Country Status (6)
Country | Link |
---|---|
EP (3) | EP3537607B1 (zh) |
JP (3) | JP2007536771A (zh) |
KR (2) | KR100999213B1 (zh) |
CN (2) | CN102055439B (zh) |
CA (2) | CA2595375A1 (zh) |
WO (1) | WO2005081758A2 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010282411A (ja) * | 2009-06-04 | 2010-12-16 | Renesas Electronics Corp | 半導体集積回路、半導体集積回路の内部状態退避回復方法 |
US8004922B2 (en) * | 2009-06-05 | 2011-08-23 | Nxp B.V. | Power island with independent power characteristics for memory and logic |
CN103548263B (zh) * | 2011-05-13 | 2016-12-07 | 株式会社半导体能源研究所 | 半导体装置 |
US8824215B2 (en) * | 2011-09-12 | 2014-09-02 | Arm Limited | Data storage circuit that retains state during precharge |
EP2982040A4 (en) | 2013-04-02 | 2017-03-29 | Hewlett-Packard Enterprise Development LP | State-retaining logic cell |
CN104517645B (zh) * | 2014-05-16 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | 闪存低速读模式控制电路 |
KR101470858B1 (ko) * | 2014-07-23 | 2014-12-09 | 주식회사 한국화이어텍 | 유무기 복합 하이브리드 수지 및 이를 이용한 코팅재 조성물 |
CN104639104B (zh) * | 2015-02-06 | 2017-03-22 | 中国人民解放军国防科学技术大学 | 功能模块级多阈值低功耗控制装置及方法 |
US11599185B2 (en) * | 2015-07-22 | 2023-03-07 | Synopsys, Inc. | Internet of things (IoT) power and performance management technique and circuit methodology |
US9859893B1 (en) * | 2016-06-30 | 2018-01-02 | Qualcomm Incorporated | High speed voltage level shifter |
CN108347241B (zh) * | 2018-01-31 | 2021-09-07 | 京微齐力(北京)科技有限公司 | 一种低功耗多路选择器的结构 |
CN108447514A (zh) * | 2018-04-02 | 2018-08-24 | 睿力集成电路有限公司 | 半导体存储器、休眠定态逻辑电路及其休眠定态方法 |
TWI674754B (zh) * | 2018-12-28 | 2019-10-11 | 新唐科技股份有限公司 | 資料保持電路 |
CN111049513B (zh) * | 2019-11-29 | 2023-08-08 | 北京时代民芯科技有限公司 | 一种带冷备份功能的轨到轨总线保持电路 |
CN112859991B (zh) * | 2021-04-23 | 2021-07-30 | 深圳市拓尔微电子有限责任公司 | 电压处理电路和控制电压处理电路的方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6246265B1 (en) * | 1998-06-12 | 2001-06-12 | Nec Corporation | Semiconductor integrated logic circuit with sequential circuits capable of preventing subthreshold leakage current |
US6337583B1 (en) * | 1999-05-17 | 2002-01-08 | Mitsubishi Denki Kabushiki Kaisha | Random logic circuit |
US6522171B2 (en) * | 2001-01-11 | 2003-02-18 | International Business Machines Corporation | Method of reducing sub-threshold leakage in circuits during standby mode |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07105174A (ja) * | 1993-10-07 | 1995-04-21 | Hitachi Ltd | 1チップマイクロコンピュータ |
JPH09261013A (ja) * | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | Dフリップフロップ回路 |
JPH10261946A (ja) * | 1997-03-19 | 1998-09-29 | Mitsubishi Electric Corp | 半導体集積回路 |
JPH11214962A (ja) * | 1997-11-19 | 1999-08-06 | Mitsubishi Electric Corp | 半導体集積回路装置 |
KR100321976B1 (ko) * | 1997-12-29 | 2002-05-13 | 윤종용 | 인텔프로세서를위한오류허용전압조절모듈회로 |
DE19811353C1 (de) * | 1998-03-16 | 1999-07-22 | Siemens Ag | Schaltungsanordnung zur Reduzierung des Leckstromes |
JP2000013215A (ja) * | 1998-04-20 | 2000-01-14 | Nec Corp | 半導体集積回路 |
JP3341681B2 (ja) * | 1998-06-12 | 2002-11-05 | 日本電気株式会社 | 半導体集積論理回路 |
US6329874B1 (en) * | 1998-09-11 | 2001-12-11 | Intel Corporation | Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode |
KR20010080575A (ko) * | 1999-09-28 | 2001-08-22 | 롤페스 요하네스 게라투스 알베르투스 | 액티브 모드와 슬립 모드에서 동작 가능한 전자 디지털 회로 |
JP2001284530A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JP2003110022A (ja) * | 2001-09-28 | 2003-04-11 | Mitsubishi Electric Corp | 半導体集積回路 |
US6538471B1 (en) * | 2001-10-10 | 2003-03-25 | International Business Machines Corporation | Multi-threshold flip-flop circuit having an outside feedback |
EP1331736A1 (en) * | 2002-01-29 | 2003-07-30 | Texas Instruments France | Flip-flop with reduced leakage current |
US6998895B2 (en) * | 2002-10-29 | 2006-02-14 | Qualcomm, Incorporated | System for reducing leakage in integrated circuits during sleep mode |
-
2005
- 2005-01-20 CN CN201010558923.0A patent/CN102055439B/zh active Active
- 2005-01-20 JP JP2006554101A patent/JP2007536771A/ja not_active Withdrawn
- 2005-01-20 KR KR1020107004248A patent/KR100999213B1/ko active IP Right Grant
- 2005-01-20 CA CA002595375A patent/CA2595375A1/en not_active Abandoned
- 2005-01-20 KR KR1020067016624A patent/KR100984406B1/ko active IP Right Grant
- 2005-01-20 CA CA2738882A patent/CA2738882C/en active Active
- 2005-01-20 WO PCT/US2005/001938 patent/WO2005081758A2/en active Application Filing
- 2005-01-20 EP EP19170964.1A patent/EP3537607B1/en active Active
- 2005-01-20 CN CN2005800054871A patent/CN1969457B/zh active Active
- 2005-01-20 EP EP05711776.4A patent/EP1743422B1/en active Active
- 2005-01-20 EP EP11177203.4A patent/EP2387156A3/en not_active Ceased
-
2011
- 2011-09-30 JP JP2011217253A patent/JP2012039644A/ja not_active Withdrawn
-
2013
- 2013-04-30 JP JP2013095072A patent/JP5671577B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6246265B1 (en) * | 1998-06-12 | 2001-06-12 | Nec Corporation | Semiconductor integrated logic circuit with sequential circuits capable of preventing subthreshold leakage current |
US6337583B1 (en) * | 1999-05-17 | 2002-01-08 | Mitsubishi Denki Kabushiki Kaisha | Random logic circuit |
US6522171B2 (en) * | 2001-01-11 | 2003-02-18 | International Business Machines Corporation | Method of reducing sub-threshold leakage in circuits during standby mode |
Non-Patent Citations (1)
Title |
---|
US 6337583 B1,全文. |
Also Published As
Publication number | Publication date |
---|---|
JP5671577B2 (ja) | 2015-02-18 |
JP2012039644A (ja) | 2012-02-23 |
JP2007536771A (ja) | 2007-12-13 |
EP2387156A3 (en) | 2013-05-29 |
CN102055439B (zh) | 2015-04-15 |
WO2005081758A3 (en) | 2006-12-07 |
CN1969457A (zh) | 2007-05-23 |
CA2595375A1 (en) | 2005-09-09 |
KR100984406B1 (ko) | 2010-09-29 |
EP3537607A1 (en) | 2019-09-11 |
JP2013179660A (ja) | 2013-09-09 |
KR20100037161A (ko) | 2010-04-08 |
EP2387156A2 (en) | 2011-11-16 |
EP1743422A2 (en) | 2007-01-17 |
WO2005081758A2 (en) | 2005-09-09 |
CN102055439A (zh) | 2011-05-11 |
EP1743422A4 (en) | 2009-05-20 |
EP3537607B1 (en) | 2022-11-23 |
CA2738882A1 (en) | 2005-09-09 |
KR20070031276A (ko) | 2007-03-19 |
CA2738882C (en) | 2016-01-12 |
KR100999213B1 (ko) | 2010-12-07 |
EP1743422B1 (en) | 2019-08-07 |
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Legal Events
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PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: KANATA, ONTARIO, CANADA TO: OTTAWA, ONTARIO, CANADA |
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CP02 | Change in the address of a patent holder |
Address after: Ontario, Canada Patentee after: SAtech Group, AB LLC Address before: California, USA Patentee before: SAtech Group, AB LLC |
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TR01 | Transfer of patent right |
Effective date of registration: 20110503 Address after: Ontario, Ottawa, Canada Patentee after: SAtech Group, AB LLC Address before: Ontario, Canada Patentee before: SAtech Group, AB LLC |
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C56 | Change in the name or address of the patentee |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. Free format text: FORMER NAME: MOSAID TECHNOLOGIES CORP. |
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CP01 | Change in the name or title of a patent holder |
Address after: Ontario, Ottawa, Canada Patentee after: MOSAID TECHNOLOGIES Inc. Address before: Ontario, Ottawa, Canada Patentee before: SAtech Group, AB LLC |