JP2007528126A5 - - Google Patents

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Publication number
JP2007528126A5
JP2007528126A5 JP2007501862A JP2007501862A JP2007528126A5 JP 2007528126 A5 JP2007528126 A5 JP 2007528126A5 JP 2007501862 A JP2007501862 A JP 2007501862A JP 2007501862 A JP2007501862 A JP 2007501862A JP 2007528126 A5 JP2007528126 A5 JP 2007528126A5
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JP
Japan
Prior art keywords
overlay
wafer
target
layers
overlay target
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007501862A
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English (en)
Japanese (ja)
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JP2007528126A (ja
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Publication date
Priority claimed from US10/790,296 external-priority patent/US7065737B2/en
Application filed filed Critical
Publication of JP2007528126A publication Critical patent/JP2007528126A/ja
Publication of JP2007528126A5 publication Critical patent/JP2007528126A5/ja
Pending legal-status Critical Current

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JP2007501862A 2004-03-01 2005-02-26 Ｉｃ製造のための複数の層のオーバーレイ測定および補正技術 Pending JP2007528126A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/790,296 US7065737B2 (en) 2004-03-01 2004-03-01 Multi-layer overlay measurement and correction technique for IC manufacturing
PCT/US2005/006178 WO2005086223A2 (en) 2004-03-01 2005-02-26 Multi-layer overlay measurement and correction technique for ic manufacturing

Publications (2)

Publication Number Publication Date
JP2007528126A JP2007528126A (ja) 2007-10-04
JP2007528126A5 true JP2007528126A5 (https=) 2009-11-05

Family

ID=34887442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007501862A Pending JP2007528126A (ja) 2004-03-01 2005-02-26 Ｉｃ製造のための複数の層のオーバーレイ測定および補正技術

Country Status (8)

Country Link
US (1) US7065737B2 (https=)
JP (1) JP2007528126A (https=)
KR (1) KR101187061B1 (https=)
CN (1) CN1926677A (https=)
DE (1) DE112005000504B4 (https=)
GB (1) GB2427268B (https=)
TW (1) TWI375251B (https=)
WO (1) WO2005086223A2 (https=)

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