JP2007511907A5 - - Google Patents

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Publication number
JP2007511907A5
JP2007511907A5 JP2006539498A JP2006539498A JP2007511907A5 JP 2007511907 A5 JP2007511907 A5 JP 2007511907A5 JP 2006539498 A JP2006539498 A JP 2006539498A JP 2006539498 A JP2006539498 A JP 2006539498A JP 2007511907 A5 JP2007511907 A5 JP 2007511907A5
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JP
Japan
Prior art keywords
forming
gate electrode
channel region
insulating film
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006539498A
Other languages
English (en)
Japanese (ja)
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JP2007511907A (ja
Filing date
Publication date
Priority claimed from US10/706,948 external-priority patent/US7074657B2/en
Application filed filed Critical
Publication of JP2007511907A publication Critical patent/JP2007511907A/ja
Publication of JP2007511907A5 publication Critical patent/JP2007511907A5/ja
Pending legal-status Critical Current

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JP2006539498A 2003-11-14 2004-10-08 完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ Pending JP2007511907A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/706,948 US7074657B2 (en) 2003-11-14 2003-11-14 Low-power multiple-channel fully depleted quantum well CMOSFETs
PCT/US2004/033413 WO2005053035A1 (en) 2003-11-14 2004-10-08 Low-power multiple-channel fully depleted quantum well cmosfets

Publications (2)

Publication Number Publication Date
JP2007511907A JP2007511907A (ja) 2007-05-10
JP2007511907A5 true JP2007511907A5 (enExample) 2007-11-29

Family

ID=34573412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006539498A Pending JP2007511907A (ja) 2003-11-14 2004-10-08 完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ

Country Status (8)

Country Link
US (2) US7074657B2 (enExample)
EP (1) EP1695389B1 (enExample)
JP (1) JP2007511907A (enExample)
KR (1) KR20060108672A (enExample)
CN (1) CN100452437C (enExample)
DE (1) DE602004027158D1 (enExample)
TW (1) TWI360225B (enExample)
WO (1) WO2005053035A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224007B1 (en) * 2004-01-12 2007-05-29 Advanced Micro Devices, Inc. Multi-channel transistor with tunable hot carrier effect
KR100549014B1 (ko) * 2004-07-21 2006-02-02 삼성전자주식회사 스페이서 패턴을 갖는 반도체 장치들 및 그 형성방법들
US7544572B2 (en) * 2005-11-30 2009-06-09 Advanced Micro Devices, Inc. Multi-operational mode transistor with multiple-channel device structure
CN102074585B (zh) * 2010-10-22 2012-07-04 友达光电股份有限公司 薄膜晶体管与显示面板
JP6401977B2 (ja) * 2013-09-06 2018-10-10 株式会社半導体エネルギー研究所 半導体装置
CN103872139B (zh) * 2014-02-24 2016-09-07 北京京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
US9653287B2 (en) * 2014-10-30 2017-05-16 Samsung Electronics Co., Ltd. S/D connection to individual channel layers in a nanosheet FET
US9590038B1 (en) 2015-10-23 2017-03-07 Samsung Electronics Co., Ltd. Semiconductor device having nanowire channel
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
KR102343470B1 (ko) 2016-01-28 2021-12-24 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN111192914B (zh) * 2017-10-18 2023-10-31 汉阳大学校产学协力团 层、多级元件、多级元件制造方法和驱动多级元件的方法
KR102814839B1 (ko) * 2019-06-11 2025-05-30 삼성전자주식회사 반도체 소자
CN112151616B (zh) * 2020-08-20 2022-12-16 中国科学院微电子研究所 一种堆叠mos器件及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153688A (en) * 1990-04-21 1992-10-06 Canon Kabushiki Kaisha Method and device for controlling interference of electron waves by light in which a transverse magnetic wave is applied
JPH04179271A (ja) * 1990-11-14 1992-06-25 Fujitsu Ltd 半導体装置及びその製造方法
TW540828U (en) * 1991-08-23 2003-07-01 Semiconductor Energy Lab Semiconductor device
JPH0575125A (ja) * 1991-09-12 1993-03-26 Toshiba Corp 薄膜トランジスタ
FR2703855B1 (fr) * 1993-04-05 1995-05-24 Valeo Electronique Montage à réponse linéarisée et symétrisée, oscillateur utilisant un tel montage et émetteur de télécommande utilisant un tel oscillateur.
JPH06310719A (ja) * 1993-04-19 1994-11-04 Sharp Corp Ｇｅ−ＳｉのＳＯＩ型ＭＯＳトランジスタ及びその製造方法
US5500545A (en) 1995-02-27 1996-03-19 United Microelectronics Corporation Double switching field effect transistor and method of manufacturing it
KR100279264B1 (ko) * 1998-12-26 2001-02-01 김영환 더블 게이트 구조를 갖는 에스·오·아이 트랜지스터 및 그의제조방법
US6373112B1 (en) * 1999-12-02 2002-04-16 Intel Corporation Polysilicon-germanium MOSFET gate electrodes
JP3527503B2 (ja) * 2000-05-31 2004-05-17 松下電器産業株式会社 半導体装置
US6432754B1 (en) 2001-02-20 2002-08-13 International Business Machines Corporation Double SOI device with recess etch and epitaxy
JP2003092400A (ja) * 2001-07-13 2003-03-28 Seiko Epson Corp 半導体装置及びその製造方法
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
FR2853454B1 (fr) * 2003-04-03 2005-07-15 St Microelectronics Sa Transistor mos haute densite
US6919250B2 (en) * 2003-05-21 2005-07-19 Advanced Micro Devices, Inc. Multiple-gate MOS device and method for making the same
US6921700B2 (en) * 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels

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