JP2007511907A - 完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ - Google Patents

完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ Download PDF

Info

Publication number
JP2007511907A
JP2007511907A JP2006539498A JP2006539498A JP2007511907A JP 2007511907 A JP2007511907 A JP 2007511907A JP 2006539498 A JP2006539498 A JP 2006539498A JP 2006539498 A JP2006539498 A JP 2006539498A JP 2007511907 A JP2007511907 A JP 2007511907A
Authority
JP
Japan
Prior art keywords
gate electrode
channel region
forming
insulating film
spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006539498A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007511907A5 (enExample
Inventor
エヌ． パン ジェイムズ
ジー． ペレリン ジョン
ディー． チーク ジョン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007511907A publication Critical patent/JP2007511907A/ja
Publication of JP2007511907A5 publication Critical patent/JP2007511907A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2006539498A 2003-11-14 2004-10-08 完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ Pending JP2007511907A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/706,948 US7074657B2 (en) 2003-11-14 2003-11-14 Low-power multiple-channel fully depleted quantum well CMOSFETs
PCT/US2004/033413 WO2005053035A1 (en) 2003-11-14 2004-10-08 Low-power multiple-channel fully depleted quantum well cmosfets

Publications (2)

Publication Number Publication Date
JP2007511907A true JP2007511907A (ja) 2007-05-10
JP2007511907A5 JP2007511907A5 (enExample) 2007-11-29

Family

ID=34573412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006539498A Pending JP2007511907A (ja) 2003-11-14 2004-10-08 完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ

Country Status (8)

Country Link
US (2) US7074657B2 (enExample)
EP (1) EP1695389B1 (enExample)
JP (1) JP2007511907A (enExample)
KR (1) KR20060108672A (enExample)
CN (1) CN100452437C (enExample)
DE (1) DE602004027158D1 (enExample)
TW (1) TWI360225B (enExample)
WO (1) WO2005053035A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009517886A (ja) * 2005-11-30 2009-04-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 複数のチャネルデバイス構造を備えたマルチ動作モードトランジスタ
US9590038B1 (en) 2015-10-23 2017-03-07 Samsung Electronics Co., Ltd. Semiconductor device having nanowire channel
KR20170046552A (ko) * 2014-10-30 2017-05-02 삼성전자주식회사 전계 효과 트랜지스터 및 그 제조 방법
JP2019212891A (ja) * 2017-10-18 2019-12-12 漢陽大学校産学協力団Ｉｎｄｕｓｔｒｙ−Ｕｎｉｖｅｒｓ 膜、マルチレベル素子、マルチレベル素子の製造方法、マルチレベル素子の駆動方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224007B1 (en) * 2004-01-12 2007-05-29 Advanced Micro Devices, Inc. Multi-channel transistor with tunable hot carrier effect
KR100549014B1 (ko) * 2004-07-21 2006-02-02 삼성전자주식회사 스페이서 패턴을 갖는 반도체 장치들 및 그 형성방법들
CN102074585B (zh) * 2010-10-22 2012-07-04 友达光电股份有限公司 薄膜晶体管与显示面板
JP6401977B2 (ja) * 2013-09-06 2018-10-10 株式会社半導体エネルギー研究所 半導体装置
CN103872139B (zh) * 2014-02-24 2016-09-07 北京京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
KR102343470B1 (ko) 2016-01-28 2021-12-24 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102814839B1 (ko) * 2019-06-11 2025-05-30 삼성전자주식회사 반도체 소자
CN112151616B (zh) * 2020-08-20 2022-12-16 中国科学院微电子研究所 一种堆叠mos器件及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04179271A (ja) * 1990-11-14 1992-06-25 Fujitsu Ltd 半導体装置及びその製造方法
JPH0575125A (ja) * 1991-09-12 1993-03-26 Toshiba Corp 薄膜トランジスタ
JP2003092400A (ja) * 2001-07-13 2003-03-28 Seiko Epson Corp 半導体装置及びその製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153688A (en) * 1990-04-21 1992-10-06 Canon Kabushiki Kaisha Method and device for controlling interference of electron waves by light in which a transverse magnetic wave is applied
TW476451U (en) * 1991-08-23 2002-02-11 Semiconductor Energy Lab Semiconductor device
FR2703855B1 (fr) * 1993-04-05 1995-05-24 Valeo Electronique Montage à réponse linéarisée et symétrisée, oscillateur utilisant un tel montage et émetteur de télécommande utilisant un tel oscillateur.
JPH06310719A (ja) * 1993-04-19 1994-11-04 Sharp Corp Ｇｅ−ＳｉのＳＯＩ型ＭＯＳトランジスタ及びその製造方法
US5500545A (en) 1995-02-27 1996-03-19 United Microelectronics Corporation Double switching field effect transistor and method of manufacturing it
KR100279264B1 (ko) * 1998-12-26 2001-02-01 김영환 더블 게이트 구조를 갖는 에스·오·아이 트랜지스터 및 그의제조방법
US6373112B1 (en) * 1999-12-02 2002-04-16 Intel Corporation Polysilicon-germanium MOSFET gate electrodes
TW475268B (en) * 2000-05-31 2002-02-01 Matsushita Electric Industrial Co Ltd Misfet
US6432754B1 (en) 2001-02-20 2002-08-13 International Business Machines Corporation Double SOI device with recess etch and epitaxy
KR100481209B1 (ko) * 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
FR2853454B1 (fr) * 2003-04-03 2005-07-15 St Microelectronics Sa Transistor mos haute densite
US6919250B2 (en) * 2003-05-21 2005-07-19 Advanced Micro Devices, Inc. Multiple-gate MOS device and method for making the same
US6921700B2 (en) * 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04179271A (ja) * 1990-11-14 1992-06-25 Fujitsu Ltd 半導体装置及びその製造方法
JPH0575125A (ja) * 1991-09-12 1993-03-26 Toshiba Corp 薄膜トランジスタ
JP2003092400A (ja) * 2001-07-13 2003-03-28 Seiko Epson Corp 半導体装置及びその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009517886A (ja) * 2005-11-30 2009-04-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 複数のチャネルデバイス構造を備えたマルチ動作モードトランジスタ
KR20170046552A (ko) * 2014-10-30 2017-05-02 삼성전자주식회사 전계 효과 트랜지스터 및 그 제조 방법
KR102370058B1 (ko) 2014-10-30 2022-03-03 삼성전자주식회사 전계 효과 트랜지스터 및 그 제조 방법
US9590038B1 (en) 2015-10-23 2017-03-07 Samsung Electronics Co., Ltd. Semiconductor device having nanowire channel
JP2019212891A (ja) * 2017-10-18 2019-12-12 漢陽大学校産学協力団Ｉｎｄｕｓｔｒｙ−Ｕｎｉｖｅｒｓ 膜、マルチレベル素子、マルチレベル素子の製造方法、マルチレベル素子の駆動方法

Also Published As

Publication number Publication date
US20050104140A1 (en) 2005-05-19
TWI360225B (en) 2012-03-11
US20060278938A1 (en) 2006-12-14
KR20060108672A (ko) 2006-10-18
EP1695389A1 (en) 2006-08-30
CN1879224A (zh) 2006-12-13
EP1695389B1 (en) 2010-05-12
CN100452437C (zh) 2009-01-14
DE602004027158D1 (de) 2010-06-24
US7074657B2 (en) 2006-07-11
WO2005053035A1 (en) 2005-06-09
TW200522356A (en) 2005-07-01
US7253484B2 (en) 2007-08-07

Similar Documents

Publication Publication Date Title
CN100573832C (zh) 制造具有多个层叠沟道的场效应晶体管的磷掺杂方法
US7309635B2 (en) Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
KR100645849B1 (ko) 반도체장치
JP2007511907A (ja) 完全に量子井戸が空乏化した低出力のマルチチャネルｃｍｏｓｆｅｔ
US11594680B2 (en) Method of forming a FinFET device
KR20250141682A (ko) 게이트 올 어라운드 나노시트 i/o 디바이스에 대한 등각 산화
JP2024102121A (ja) 水平ゲートオールアラウンド（ｈＧＡＡ）ナノワイヤ及びナノスラブトランジスタ
US20080093666A1 (en) Semiconductor Device and Manufacturing Method Thereof
US20220352321A1 (en) Method of Forming a Semiconductor Device with Implantation of Impurities at High Temperature
US20250056871A1 (en) Methods of forming bottom dielectric isolation layers
TW202247463A (zh) 具全空乏矽晶絕緣體之環繞式閘極元件
JP7787284B2 (ja) 底部誘電体を有するナノシートのソースドレイン形成のためのテンプレート
TW202338939A (zh) 形成半導體元件的方法
US7618868B2 (en) Method of manufacturing field effect transistors using sacrificial blocking layers
JP4011014B2 (ja) 半導体装置およびその製造方法
US6919250B2 (en) Multiple-gate MOS device and method for making the same
JP2025535289A (ja) 金属ソース／ドレイン水平ゲート・オール・アラウンドアーキテクチャ用の犠牲ソース／ドレイン
JP2006120801A (ja) 半導体装置及びその製造方法
JP2010056239A (ja) 半導体装置及び半導体装置の製造方法
JP2004031529A (ja) 半導体装置及びその製造方法
JP2002217411A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071009

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071009

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110623

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110629

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111130