JP2007335581A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2007335581A
JP2007335581A JP2006164822A JP2006164822A JP2007335581A JP 2007335581 A JP2007335581 A JP 2007335581A JP 2006164822 A JP2006164822 A JP 2006164822A JP 2006164822 A JP2006164822 A JP 2006164822A JP 2007335581 A JP2007335581 A JP 2007335581A
Authority
JP
Japan
Prior art keywords
wiring
semiconductor device
manufacturing
main surface
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006164822A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007335581A5 (enExample
Inventor
Tetsuji Tagami
哲治 田上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2006164822A priority Critical patent/JP2007335581A/ja
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to TW096114262A priority patent/TW200807666A/zh
Priority to CNA2007101065554A priority patent/CN101090081A/zh
Priority to US11/759,290 priority patent/US7659146B2/en
Priority to KR1020070057541A priority patent/KR101296572B1/ko
Publication of JP2007335581A publication Critical patent/JP2007335581A/ja
Publication of JP2007335581A5 publication Critical patent/JP2007335581A5/ja
Priority to US12/545,964 priority patent/US7915086B2/en
Priority to US13/021,284 priority patent/US8048722B2/en
Priority to US13/226,607 priority patent/US8258018B2/en
Priority to US13/551,487 priority patent/US8420451B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2006164822A 2006-06-14 2006-06-14 半導体装置の製造方法 Pending JP2007335581A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2006164822A JP2007335581A (ja) 2006-06-14 2006-06-14 半導体装置の製造方法
TW096114262A TW200807666A (en) 2006-06-14 2007-04-23 Manufacturing Method of Semiconductor Device
CNA2007101065554A CN101090081A (zh) 2006-06-14 2007-06-06 半导体器件的制造方法
US11/759,290 US7659146B2 (en) 2006-06-14 2007-06-07 Manufacturing method of semiconductor device
KR1020070057541A KR101296572B1 (ko) 2006-06-14 2007-06-13 반도체 장치의 제조 방법
US12/545,964 US7915086B2 (en) 2006-06-14 2009-08-24 Manufacturing method of semiconductor device
US13/021,284 US8048722B2 (en) 2006-06-14 2011-02-04 Manufacturing method of semiconductor device
US13/226,607 US8258018B2 (en) 2006-06-14 2011-09-07 Manufacturing method of semiconductor device
US13/551,487 US8420451B2 (en) 2006-06-14 2012-07-17 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006164822A JP2007335581A (ja) 2006-06-14 2006-06-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2007335581A true JP2007335581A (ja) 2007-12-27
JP2007335581A5 JP2007335581A5 (enExample) 2009-07-16

Family

ID=38862090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006164822A Pending JP2007335581A (ja) 2006-06-14 2006-06-14 半導体装置の製造方法

Country Status (5)

Country Link
US (5) US7659146B2 (enExample)
JP (1) JP2007335581A (enExample)
KR (1) KR101296572B1 (enExample)
CN (1) CN101090081A (enExample)
TW (1) TW200807666A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012079854A (ja) * 2010-09-30 2012-04-19 Renesas Electronics Corp 半導体装置の製造方法
JP2016122802A (ja) * 2014-12-25 2016-07-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2017069573A (ja) * 2016-12-12 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5692952B2 (ja) * 2007-12-11 2015-04-01 シチズン電子株式会社 発光ダイオード
JP5188289B2 (ja) * 2008-06-26 2013-04-24 ラピスセミコンダクタ株式会社 プリント基板の製造方法
US8749074B2 (en) * 2009-11-30 2014-06-10 Micron Technology, Inc. Package including an interposer having at least one topological feature
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
JP6068175B2 (ja) * 2013-02-12 2017-01-25 新光電気工業株式会社 配線基板、発光装置、配線基板の製造方法及び発光装置の製造方法
KR20160000293A (ko) * 2014-06-24 2016-01-04 삼성전자주식회사 탭 핀에 타이바가 없는 반도체 모듈
US10879160B2 (en) * 2018-02-01 2020-12-29 SK Hynix Inc. Semiconductor package with packaging substrate
CN110112117A (zh) * 2018-02-01 2019-08-09 爱思开海力士有限公司 半导体封装
KR102509051B1 (ko) * 2018-02-01 2023-03-10 에스케이하이닉스 주식회사 반도체 패키지
KR20190093488A (ko) * 2018-02-01 2019-08-09 에스케이하이닉스 주식회사 반도체 패키지
CN110112116B (zh) * 2018-02-01 2023-06-06 爱思开海力士有限公司 半导体封装件和形成半导体封装件的方法
US11462501B2 (en) * 2019-10-25 2022-10-04 Shinko Electric Industries Co., Ltd. Interconnect substrate and method of making the same
CN116130445A (zh) * 2021-11-12 2023-05-16 合肥本源量子计算科技有限责任公司 一种量子器件及其制备方法、一种量子计算机

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450450A (en) * 1987-08-20 1989-02-27 Toshiba Corp Package for semiconductor integrated circuit
JP2001068588A (ja) * 1999-08-26 2001-03-16 Nec Corp パッケージ基板、該パッケージ基板を備える半導体装置及びそれらの製造方法
JP2002050715A (ja) * 2000-08-03 2002-02-15 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法
JP2003086735A (ja) * 2001-06-27 2003-03-20 Shinko Electric Ind Co Ltd 位置情報付配線基板及びその製造方法並びに半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3619773B2 (ja) * 2000-12-20 2005-02-16 株式会社ルネサステクノロジ 半導体装置の製造方法
WO2002103793A1 (en) * 2001-06-07 2002-12-27 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
EP1280204A3 (en) * 2001-06-27 2004-09-01 Shinko Electric Industries Co. Ltd. Wiring substrate having position problem
JP2005079129A (ja) 2003-08-28 2005-03-24 Sumitomo Metal Electronics Devices Inc プラスチックパッケージ及びその製造方法
KR100557540B1 (ko) * 2004-07-26 2006-03-03 삼성전기주식회사 Ｂｇａ 패키지 기판 및 그 제작 방법
JP4651359B2 (ja) 2004-10-29 2011-03-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2006261485A (ja) * 2005-03-18 2006-09-28 Renesas Technology Corp 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450450A (en) * 1987-08-20 1989-02-27 Toshiba Corp Package for semiconductor integrated circuit
JP2001068588A (ja) * 1999-08-26 2001-03-16 Nec Corp パッケージ基板、該パッケージ基板を備える半導体装置及びそれらの製造方法
JP2002050715A (ja) * 2000-08-03 2002-02-15 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法
JP2003086735A (ja) * 2001-06-27 2003-03-20 Shinko Electric Ind Co Ltd 位置情報付配線基板及びその製造方法並びに半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012079854A (ja) * 2010-09-30 2012-04-19 Renesas Electronics Corp 半導体装置の製造方法
US8389339B2 (en) 2010-09-30 2013-03-05 Renesas Electronics Corporation Method of manufacturing semiconductor device
JP2016122802A (ja) * 2014-12-25 2016-07-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2017069573A (ja) * 2016-12-12 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
KR101296572B1 (ko) 2013-08-13
US8420451B2 (en) 2013-04-16
US8258018B2 (en) 2012-09-04
TW200807666A (en) 2008-02-01
US20110124159A1 (en) 2011-05-26
US7915086B2 (en) 2011-03-29
US20120282737A1 (en) 2012-11-08
US8048722B2 (en) 2011-11-01
CN101090081A (zh) 2007-12-19
US20070292993A1 (en) 2007-12-20
KR20070119521A (ko) 2007-12-20
US7659146B2 (en) 2010-02-09
US20090311833A1 (en) 2009-12-17
US20120083072A1 (en) 2012-04-05

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