JP2007335581A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2007335581A
JP2007335581A JP2006164822A JP2006164822A JP2007335581A JP 2007335581 A JP2007335581 A JP 2007335581A JP 2006164822 A JP2006164822 A JP 2006164822A JP 2006164822 A JP2006164822 A JP 2006164822A JP 2007335581 A JP2007335581 A JP 2007335581A
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Japan
Prior art keywords
wiring
semiconductor device
manufacturing
main surface
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2006164822A
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English (en)
Japanese (ja)
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JP2007335581A5 (enExample
Inventor
Tetsuji Tagami
哲治 田上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to JP2006164822A priority Critical patent/JP2007335581A/ja
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to TW096114262A priority patent/TW200807666A/zh
Priority to CNA2007101065554A priority patent/CN101090081A/zh
Priority to US11/759,290 priority patent/US7659146B2/en
Priority to KR1020070057541A priority patent/KR101296572B1/ko
Publication of JP2007335581A publication Critical patent/JP2007335581A/ja
Publication of JP2007335581A5 publication Critical patent/JP2007335581A5/ja
Priority to US12/545,964 priority patent/US7915086B2/en
Priority to US13/021,284 priority patent/US8048722B2/en
Priority to US13/226,607 priority patent/US8258018B2/en
Priority to US13/551,487 priority patent/US8420451B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2006164822A 2006-06-14 2006-06-14 半導体装置の製造方法 Pending JP2007335581A (ja)

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Application Number Priority Date Filing Date Title
JP2006164822A JP2007335581A (ja) 2006-06-14 2006-06-14 半導体装置の製造方法
TW096114262A TW200807666A (en) 2006-06-14 2007-04-23 Manufacturing Method of Semiconductor Device
CNA2007101065554A CN101090081A (zh) 2006-06-14 2007-06-06 半导体器件的制造方法
US11/759,290 US7659146B2 (en) 2006-06-14 2007-06-07 Manufacturing method of semiconductor device
KR1020070057541A KR101296572B1 (ko) 2006-06-14 2007-06-13 반도체 장치의 제조 방법
US12/545,964 US7915086B2 (en) 2006-06-14 2009-08-24 Manufacturing method of semiconductor device
US13/021,284 US8048722B2 (en) 2006-06-14 2011-02-04 Manufacturing method of semiconductor device
US13/226,607 US8258018B2 (en) 2006-06-14 2011-09-07 Manufacturing method of semiconductor device
US13/551,487 US8420451B2 (en) 2006-06-14 2012-07-17 Manufacturing method of semiconductor device

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JP2012079854A (ja) * 2010-09-30 2012-04-19 Renesas Electronics Corp 半導体装置の製造方法
JP2016122802A (ja) * 2014-12-25 2016-07-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2017069573A (ja) * 2016-12-12 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

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JP5188289B2 (ja) * 2008-06-26 2013-04-24 ラピスセミコンダクタ株式会社 プリント基板の製造方法
US8749074B2 (en) * 2009-11-30 2014-06-10 Micron Technology, Inc. Package including an interposer having at least one topological feature
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
JP6068175B2 (ja) * 2013-02-12 2017-01-25 新光電気工業株式会社 配線基板、発光装置、配線基板の製造方法及び発光装置の製造方法
KR20160000293A (ko) * 2014-06-24 2016-01-04 삼성전자주식회사 탭 핀에 타이바가 없는 반도체 모듈
CN110112117A (zh) * 2018-02-01 2019-08-09 爱思开海力士有限公司 半导体封装
KR20190093488A (ko) * 2018-02-01 2019-08-09 에스케이하이닉스 주식회사 반도체 패키지
US10879160B2 (en) * 2018-02-01 2020-12-29 SK Hynix Inc. Semiconductor package with packaging substrate
CN110112116B (zh) 2018-02-01 2023-06-06 爱思开海力士有限公司 半导体封装件和形成半导体封装件的方法
KR102509051B1 (ko) * 2018-02-01 2023-03-10 에스케이하이닉스 주식회사 반도체 패키지
US11462501B2 (en) * 2019-10-25 2022-10-04 Shinko Electric Industries Co., Ltd. Interconnect substrate and method of making the same
CN116130445A (zh) * 2021-11-12 2023-05-16 合肥本源量子计算科技有限责任公司 一种量子器件及其制备方法、一种量子计算机

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JP2002050715A (ja) * 2000-08-03 2002-02-15 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法
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JP2012079854A (ja) * 2010-09-30 2012-04-19 Renesas Electronics Corp 半導体装置の製造方法
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JP2016122802A (ja) * 2014-12-25 2016-07-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2017069573A (ja) * 2016-12-12 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

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CN101090081A (zh) 2007-12-19
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US20090311833A1 (en) 2009-12-17
US7915086B2 (en) 2011-03-29
KR20070119521A (ko) 2007-12-20
US7659146B2 (en) 2010-02-09
US8048722B2 (en) 2011-11-01
KR101296572B1 (ko) 2013-08-13
US20110124159A1 (en) 2011-05-26
US8420451B2 (en) 2013-04-16
US20120282737A1 (en) 2012-11-08
US20120083072A1 (en) 2012-04-05
TW200807666A (en) 2008-02-01

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