JP2007273550A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP2007273550A JP2007273550A JP2006094702A JP2006094702A JP2007273550A JP 2007273550 A JP2007273550 A JP 2007273550A JP 2006094702 A JP2006094702 A JP 2006094702A JP 2006094702 A JP2006094702 A JP 2006094702A JP 2007273550 A JP2007273550 A JP 2007273550A
- Authority
- JP
- Japan
- Prior art keywords
- region
- annealing
- semiconductor substrate
- concentration
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
ボロン(B)を浅く、高濃度にドープすることのできる半導体装置の製造方法を提供する。
【解決手段】
半導体装置の製造方法は、(a)半導体基板にボロン(B)をイオン注入する工程と、(b)半導体基板にフッ素(F)または窒素(N)をイオン注入する工程と、(c)工程(a)、(b)を行った後、半導体基板のイオン注入を行った領域に加熱時間が100msec以下であるアニールを行う工程と、(d)工程(c)の後、半導体基板のイオン注入を行った領域にアニールを行う工程と、を含む。
【選択図】 図2
Description
(a)半導体基板にボロン(B)をイオン注入する工程と、
(b)前記半導体基板にフッ素(F)または窒素(N)をイオン注入する工程と、
(c)前記工程(a)、(b)を行った後、前記半導体基板のイオン注入を行った領域にmsecアニールを行う工程と、
(d)前記工程(c)の後、前記半導体基板のイオン注入を行った領域にスパイクアニールを行う工程と、
を含む半導体装置の製造方法
が提供される。
半導体基板と、
前記半導体基板中に形成されたp型領域であって、ボロン(B)とフッ素(F)または窒素(N)とを含み、B濃度が半導体基板表面から深さと共に急速に減少し、キンクを形成してなだらかな減少に転じるキンクの深さでのB濃度が2×1020cm−3以上であるp型領域と、
を有する半導体装置
が提供される。
(a)半導体基板に不純物をイオン注入する工程と、
(b)前記工程(a)を行った後、前記半導体基板のイオン注入を行った領域にmsecアニールを行う工程と、
(c)前記工程(b)の後、他のイオン注入を行う前に、前記半導体基板のイオン注入を行った領域にスパイクアニールを行う工程と、
を含む半導体装置の製造方法
が提供される。
図8Gに示すように、活性領域3,4にRTAによるアニール処理を行う。アニール条件としては、加熱温度900℃〜1050℃で加熱時間ほぼ0秒とし、窒素雰囲気中で行う。以後、第1の実施例同様、図6I以下のサイドウォール形成、ディープS/D形成用イオン注入、RTAによる活性化アニール、配線形成等の工程を行う。
2 STI
3、4 活性領域
5 ゲート絶縁膜
6 ゲート電極
7,8 レジストマスク
9 サイドウォール
11 p型ポケット領域
13 n型エクステンション領域
14 n型ポケット領域
15 Fドープ領域
16 p型エクステンション領域
17 n型ディープS/D領域
18 p型ディープS/D領域
S サンプル
St ステップ
Claims (10)
- (a)半導体基板にボロン(B)をイオン注入する工程と、
(b)前記半導体基板にフッ素(F)または窒素(N)をイオン注入する工程と、
(c)前記工程(a)、(b)を行った後、前記半導体基板のイオン注入を行った領域に加熱時間が100msec以下である第1のアニールを行う工程と、
(d)前記工程(c)の後、前記半導体基板のイオン注入を行った領域に第2のアニールを行う工程と、
を含む半導体装置の製造方法。 - (e)前記工程(a)、(b)の前に、前記半導体基板表面に絶縁ゲート構造を形成する工程、
をさらに含む請求項1記載の半導体装置の製造方法。 - 前記半導体基板がn型活性領域を有し、前記工程(e)が前記n型活性領域上に前記絶縁ゲート構造を形成し、前記工程(a)が、前記絶縁ゲート構造両側の前記n型活性領域にpチャネルトランジスタのソース/ドレインのエクステンション領域を形成する請求項2記載の半導体装置の製造方法。
- (f)前記工程(e)の後、前記n型活性領域中に前記エクステンション領域より深くn型ポケット領域のイオン注入を行う工程、
をさらに含む請求項3記載の半導体装置の製造方法。 - 前記半導体基板がp型活性領域を有し、前記工程(e)が前記p型活性領域上に前記絶縁ゲート構造を形成し、前記工程(a)が、前記絶縁ゲート構造両側の前記p型活性領域にnチャネルトランジスタのp型ポケット領域を形成する請求項2記載の半導体装置の製造方法。
- 前記工程(a)と(b)とが、BFまたはBF2をイオン注入することで同時に行われる請求項1〜5のいずれか1項記載の半導体装置の製造方法。
- 半導体基板と、
前記半導体基板中に形成されたp型領域であって、ボロン(B)とフッ素(F)または窒素(N)とを含み、B濃度が半導体基板表面から深さと共に急速に減少し、キンクを形成してなだらかな減少に転じるキンクの深さでのB濃度が2×1020cm−3以上であるp型領域と、
を有する半導体装置。 - 前記半導体基板がn型活性領域を有し、
前記n型活性領域表面上に形成された絶縁ゲート電極、
をさらに有し、前記p型領域が前記絶縁ゲート電極両側に形成されたソース/ドレインのエクステンション領域である請求項7記載の半導体装置。 - 前記エクステンション領域を包むように形成されたn型ポケット領域、
をさらに含む請求項8記載の半導体装置。 - (a)半導体基板に不純物をイオン注入する工程と、
(b)前記工程(a)を行った後、前記半導体基板のイオン注入を行った領域に加熱時間が100msec以下である第1のアニールを行う工程と、
(c)前記工程(b)の後、他のイオン注入を行う前に、前記半導体基板のイオン注入を行った領域に前記第1のアニールの加熱時間より長い加熱時間の第2のアニールを行う工程と、
を含む半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006094702A JP5283827B2 (ja) | 2006-03-30 | 2006-03-30 | 半導体装置の製造方法 |
US11/607,927 US7645665B2 (en) | 2006-03-30 | 2006-12-04 | Semiconductor device having shallow b-doped region and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006094702A JP5283827B2 (ja) | 2006-03-30 | 2006-03-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007273550A true JP2007273550A (ja) | 2007-10-18 |
JP5283827B2 JP5283827B2 (ja) | 2013-09-04 |
Family
ID=38559705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006094702A Expired - Fee Related JP5283827B2 (ja) | 2006-03-30 | 2006-03-30 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7645665B2 (ja) |
JP (1) | JP5283827B2 (ja) |
Families Citing this family (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100783283B1 (ko) * | 2006-12-05 | 2007-12-06 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
DE102007020260B4 (de) * | 2007-04-30 | 2010-04-08 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Verbessern der Transistoreigenschaften von Feldeffekttransistoren durch eine späte tiefe Implantation in Verbindung mit einem diffusionsfreien Ausheizprozess |
US7906405B2 (en) * | 2007-12-24 | 2011-03-15 | Texas Instruments Incorporated | Polysilicon structures resistant to laser anneal lightpipe waveguide effects |
JP2009182076A (ja) * | 2008-01-30 | 2009-08-13 | Panasonic Corp | 半導体装置及びその製造方法 |
US8278197B2 (en) * | 2008-05-30 | 2012-10-02 | International Business Machines Corporation | Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device |
US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
US20110079861A1 (en) * | 2009-09-30 | 2011-04-07 | Lucian Shifren | Advanced Transistors with Threshold Voltage Set Dopant Structures |
US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
EP2360717B1 (en) * | 2009-12-09 | 2012-03-28 | ABB Technology AG | Method for producing a semiconductor device using laser annealing for selectively activating implanted dopants |
CN102194748B (zh) * | 2010-03-15 | 2014-04-16 | 北京大学 | 半导体器件及其制造方法 |
US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
US8569128B2 (en) | 2010-06-21 | 2013-10-29 | Suvolta, Inc. | Semiconductor structure and method of fabrication thereof with mixed metal types |
US8759872B2 (en) | 2010-06-22 | 2014-06-24 | Suvolta, Inc. | Transistor with threshold voltage set notch and method of fabrication thereof |
JP5527080B2 (ja) * | 2010-07-22 | 2014-06-18 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8377783B2 (en) | 2010-09-30 | 2013-02-19 | Suvolta, Inc. | Method for reducing punch-through in a transistor device |
US8404551B2 (en) | 2010-12-03 | 2013-03-26 | Suvolta, Inc. | Source/drain extension control for advanced transistors |
US8461875B1 (en) | 2011-02-18 | 2013-06-11 | Suvolta, Inc. | Digital circuits having improved transistors, and methods therefor |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8400219B2 (en) | 2011-03-24 | 2013-03-19 | Suvolta, Inc. | Analog circuits having improved transistors, and methods therefor |
US8748270B1 (en) | 2011-03-30 | 2014-06-10 | Suvolta, Inc. | Process for manufacturing an improved analog transistor |
US8993451B2 (en) * | 2011-04-15 | 2015-03-31 | Freescale Semiconductor, Inc. | Etching trenches in a substrate |
US8999861B1 (en) | 2011-05-11 | 2015-04-07 | Suvolta, Inc. | Semiconductor structure with substitutional boron and method for fabrication thereof |
US8796048B1 (en) | 2011-05-11 | 2014-08-05 | Suvolta, Inc. | Monitoring and measurement of thin film layers |
US8811068B1 (en) | 2011-05-13 | 2014-08-19 | Suvolta, Inc. | Integrated circuit devices and methods |
US8569156B1 (en) | 2011-05-16 | 2013-10-29 | Suvolta, Inc. | Reducing or eliminating pre-amorphization in transistor manufacture |
KR20120133652A (ko) * | 2011-05-31 | 2012-12-11 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8995204B2 (en) | 2011-06-23 | 2015-03-31 | Suvolta, Inc. | Circuit devices and methods having adjustable transistor body bias |
US8629016B1 (en) | 2011-07-26 | 2014-01-14 | Suvolta, Inc. | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
WO2013022753A2 (en) | 2011-08-05 | 2013-02-14 | Suvolta, Inc. | Semiconductor devices having fin structures and fabrication methods thereof |
US8748986B1 (en) | 2011-08-05 | 2014-06-10 | Suvolta, Inc. | Electronic device with controlled threshold voltage |
US8884341B2 (en) * | 2011-08-16 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits |
US8614128B1 (en) | 2011-08-23 | 2013-12-24 | Suvolta, Inc. | CMOS structures and processes based on selective thinning |
US8645878B1 (en) | 2011-08-23 | 2014-02-04 | Suvolta, Inc. | Porting a circuit design from a first semiconductor process to a second semiconductor process |
US8713511B1 (en) | 2011-09-16 | 2014-04-29 | Suvolta, Inc. | Tools and methods for yield-aware semiconductor manufacturing process target generation |
US9236466B1 (en) | 2011-10-07 | 2016-01-12 | Mie Fujitsu Semiconductor Limited | Analog circuits having improved insulated gate transistors, and methods therefor |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US8819603B1 (en) | 2011-12-15 | 2014-08-26 | Suvolta, Inc. | Memory circuits and methods of making and designing the same |
US8883600B1 (en) | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
US8599623B1 (en) | 2011-12-23 | 2013-12-03 | Suvolta, Inc. | Circuits and methods for measuring circuit elements in an integrated circuit device |
US8877619B1 (en) | 2012-01-23 | 2014-11-04 | Suvolta, Inc. | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
US8970289B1 (en) | 2012-01-23 | 2015-03-03 | Suvolta, Inc. | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
US9093550B1 (en) | 2012-01-31 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
US9406567B1 (en) | 2012-02-28 | 2016-08-02 | Mie Fujitsu Semiconductor Limited | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
US8863064B1 (en) | 2012-03-23 | 2014-10-14 | Suvolta, Inc. | SRAM cell layout structure and devices therefrom |
US9299698B2 (en) | 2012-06-27 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Semiconductor structure with multiple transistors having various threshold voltages |
US8637955B1 (en) | 2012-08-31 | 2014-01-28 | Suvolta, Inc. | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
US9112057B1 (en) | 2012-09-18 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
US9041126B2 (en) | 2012-09-21 | 2015-05-26 | Mie Fujitsu Semiconductor Limited | Deeply depleted MOS transistors having a screening layer and methods thereof |
JP2016500927A (ja) | 2012-10-31 | 2016-01-14 | 三重富士通セミコンダクター株式会社 | 低変動トランジスタ・ペリフェラル回路を備えるdram型デバイス、及び関連する方法 |
US8816754B1 (en) | 2012-11-02 | 2014-08-26 | Suvolta, Inc. | Body bias circuits and methods |
US9093997B1 (en) | 2012-11-15 | 2015-07-28 | Mie Fujitsu Semiconductor Limited | Slew based process and bias monitors and related methods |
US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
US9112484B1 (en) | 2012-12-20 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit process and bias monitors and related methods |
US9268885B1 (en) | 2013-02-28 | 2016-02-23 | Mie Fujitsu Semiconductor Limited | Integrated circuit device methods and models with predicted device metric variations |
US8994415B1 (en) | 2013-03-01 | 2015-03-31 | Suvolta, Inc. | Multiple VDD clock buffer |
US8988153B1 (en) | 2013-03-09 | 2015-03-24 | Suvolta, Inc. | Ring oscillator with NMOS or PMOS variation insensitivity |
US9299801B1 (en) | 2013-03-14 | 2016-03-29 | Mie Fujitsu Semiconductor Limited | Method for fabricating a transistor device with a tuned dopant profile |
US9112495B1 (en) | 2013-03-15 | 2015-08-18 | Mie Fujitsu Semiconductor Limited | Integrated circuit device body bias circuits and methods |
US9449967B1 (en) | 2013-03-15 | 2016-09-20 | Fujitsu Semiconductor Limited | Transistor array structure |
US9478571B1 (en) | 2013-05-24 | 2016-10-25 | Mie Fujitsu Semiconductor Limited | Buried channel deeply depleted channel transistor |
US8976575B1 (en) | 2013-08-29 | 2015-03-10 | Suvolta, Inc. | SRAM performance monitor |
US9710006B2 (en) | 2014-07-25 | 2017-07-18 | Mie Fujitsu Semiconductor Limited | Power up body bias circuits and methods |
US9319013B2 (en) | 2014-08-19 | 2016-04-19 | Mie Fujitsu Semiconductor Limited | Operational amplifier input offset correction with transistor threshold voltage adjustment |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002329864A (ja) * | 2001-03-02 | 2002-11-15 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2003528462A (ja) * | 2000-03-17 | 2003-09-24 | バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド | レーザーアニーリングおよび急速熱アニーリングにより極めて浅い接合を形成する方法 |
JP2003309079A (ja) * | 2002-04-16 | 2003-10-31 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2004228528A (ja) * | 2003-01-27 | 2004-08-12 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2004289125A (ja) * | 2003-03-04 | 2004-10-14 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005524988A (ja) * | 2002-05-09 | 2005-08-18 | バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド | ダメージと抵抗の小さいウルトラシャロージャンクションを形成する方法 |
JP2006059843A (ja) * | 2004-08-17 | 2006-03-02 | Toshiba Corp | 半導体装置とその製造方法 |
JP2006073728A (ja) * | 2004-09-01 | 2006-03-16 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2006279013A (ja) * | 2005-03-03 | 2006-10-12 | Nec Electronics Corp | 電界効果型トランジスタの製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4818499B2 (ja) * | 2000-09-01 | 2011-11-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4236992B2 (ja) | 2002-06-24 | 2009-03-11 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
WO2004068588A1 (ja) * | 2003-01-31 | 2004-08-12 | Fujitsu Limited | 半導体装置及びその製造方法 |
JP4733912B2 (ja) * | 2003-04-03 | 2011-07-27 | 株式会社東芝 | 半導体装置の製造方法 |
JP2005005406A (ja) * | 2003-06-10 | 2005-01-06 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
JP2005136382A (ja) | 2003-10-09 | 2005-05-26 | Toshiba Corp | 半導体装置の製造方法 |
JP2005142344A (ja) | 2003-11-06 | 2005-06-02 | Toshiba Corp | 半導体装置の製造方法および半導体製造装置 |
US6989322B2 (en) * | 2003-11-25 | 2006-01-24 | International Business Machines Corporation | Method of forming ultra-thin silicidation-stop extensions in mosfet devices |
JP4594664B2 (ja) * | 2004-07-07 | 2010-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006086467A (ja) * | 2004-09-17 | 2006-03-30 | Toshiba Corp | 半導体装置及びその製造方法 |
US20070072382A1 (en) * | 2005-09-28 | 2007-03-29 | Fujitsu Limited | Method of manufacturing semiconductor device |
-
2006
- 2006-03-30 JP JP2006094702A patent/JP5283827B2/ja not_active Expired - Fee Related
- 2006-12-04 US US11/607,927 patent/US7645665B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003528462A (ja) * | 2000-03-17 | 2003-09-24 | バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド | レーザーアニーリングおよび急速熱アニーリングにより極めて浅い接合を形成する方法 |
JP2002329864A (ja) * | 2001-03-02 | 2002-11-15 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2003309079A (ja) * | 2002-04-16 | 2003-10-31 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2005524988A (ja) * | 2002-05-09 | 2005-08-18 | バリアン・セミコンダクター・エクイップメント・アソシエイツ・インコーポレイテッド | ダメージと抵抗の小さいウルトラシャロージャンクションを形成する方法 |
JP2004228528A (ja) * | 2003-01-27 | 2004-08-12 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2004289125A (ja) * | 2003-03-04 | 2004-10-14 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006059843A (ja) * | 2004-08-17 | 2006-03-02 | Toshiba Corp | 半導体装置とその製造方法 |
JP2006073728A (ja) * | 2004-09-01 | 2006-03-16 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2006279013A (ja) * | 2005-03-03 | 2006-10-12 | Nec Electronics Corp | 電界効果型トランジスタの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7645665B2 (en) | 2010-01-12 |
JP5283827B2 (ja) | 2013-09-04 |
US20070232039A1 (en) | 2007-10-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5283827B2 (ja) | 半導体装置の製造方法 | |
US7682892B2 (en) | MOS device and process having low resistance silicide interface using additional source/drain implant | |
JP2002329864A (ja) | 半導体装置及びその製造方法 | |
JP2009272423A (ja) | 半導体装置及びその製造方法 | |
US6972222B2 (en) | Temporary self-aligned stop layer is applied on silicon sidewall | |
JP2006059843A (ja) | 半導体装置とその製造方法 | |
JP2010021525A (ja) | 半導体装置の製造方法 | |
JP5401803B2 (ja) | 半導体装置の製造方法 | |
JP5303881B2 (ja) | 電界効果トランジスタ及び電界効果トランジスタの製造方法 | |
US20080286929A1 (en) | Method for manufacturing semiconductor device | |
KR100540490B1 (ko) | 플러그이온주입을 포함하는 반도체소자의 콘택 형성 방법 | |
JP2006245338A (ja) | 電界効果型トランジスタの製造方法 | |
JPWO2004114413A1 (ja) | 半導体装置及びその製造方法 | |
US7211489B1 (en) | Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal | |
KR100873240B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP4795759B2 (ja) | 電界効果型トランジスタの製造方法 | |
JP5338042B2 (ja) | 電界効果トランジスタの製造方法 | |
KR100549573B1 (ko) | 모스형 트랜지스터의 제조방법 | |
KR100503743B1 (ko) | 반도체 소자 제조 방법 | |
KR100588784B1 (ko) | 반도체 소자 제조방법 | |
KR101051954B1 (ko) | 반도체 소자의 트랜지스터 형성방법 | |
KR100720405B1 (ko) | 반도체 소자의 제조방법 | |
KR100740780B1 (ko) | 반도체 소자의 트랜지스터 제조 방법 | |
KR100824661B1 (ko) | 반도체 소자의 제조방법 | |
KR100477832B1 (ko) | 데카보렌을 이용한 플러그 이온주입을 포함하는 피모스트랜지스터의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081015 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111007 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111018 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111216 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120228 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130201 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130529 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5283827 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |