JP2007165350A - 半導体装置の製造方法 - Google Patents
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Abstract
【解決手段】半導体基板10上及び強誘電体キャパシタ42上に第1の絶縁膜48を形成する工程と、第1の配線56a〜56cを形成する工程と、第2の絶縁膜60を形成する工程と、第2の絶縁膜の表面を平坦化する工程と、熱処理炉を用いて熱処理を行うことにより第2の絶縁膜中から水分を除去する工程と、N2Oガス又はN2ガスを用いて生成されたプラズマ雰囲気中にて熱処理を行うことにより、第2の絶縁膜中から水分を除去するとともに第2の絶縁膜の表面を窒化する工程と、第2の絶縁膜上にバリア膜62を形成する工程と、バリア膜及び第2の絶縁膜にコンタクトホール68を形成する工程と、コンタクトホール内に導体プラグ70を埋め込む工程とを有している。
【選択図】 図12
Description
平坦なバリア膜は、被覆性が極めて良好であるため、水分等をバリアする機能が極めて高い。このため、層間絶縁膜中に水分がある程度残存している状態で、層間絶縁膜上に平坦なバリア膜が形成され、この後、層間絶縁膜に熱が加わった場合には、層間絶縁膜中からの水分の放出がバリア膜により閉じ込められた状態となる。このため、層間絶縁膜及びバリア膜にコンタクトホールが形成されている状態で層間絶縁膜に熱が加わった場合には、層間絶縁膜中の水分がコンタクトホールを介して大量に放出される。コンタクトホール内にCVD法により導体プラグを埋め込む際には層間絶縁膜に熱が加わるため、層間絶縁膜中の水分がコンタクトホールを介して大量に放出される。導体プラグを埋め込む際に層間絶縁膜中の水分がコンタクトホールを介して大量に放出されると、導体プラグを形成するための原料ガスがコンタクトホール内に到達することが阻害される。そうすると、コンタクトホール内に導体プラグが良好に形成されず、信頼性の低下を招いてしまうこととなる。
本発明の一実施形態による半導体装置の製造方法を図3乃至図17を用いて説明する。
まず、本実施形態による半導体装置の構造について図3を用いて説明する。図3は、本実施形態による半導体装置を示す断面図である。
次に、本実施形態による半導体装置の製造方法について図4乃至図17を用いて説明する。図4乃至図17は、本実施形態による半導体装置の製造方法を示す工程断面図である。
本発明は上記実施形態に限らず種々の変形が可能である。
12…素子分離領域
14a、14b…ウェル
16…ゲート絶縁膜
18…ゲート電極
19…絶縁膜
20…サイドウォール絶縁膜
22…ソース/ドレイン拡散層
24…トランジスタ
25…SiON膜
26…シリコン酸化膜
27…層間絶縁膜
34…シリコン酸化膜
36…下部電極
36a…酸化アルミニウム膜
36b…Pt膜
38…強誘電体膜
40…上部電極
40a…IrOX膜
40b…IrOY膜
42…強誘電体キャパシタ
44…バリア膜
46…バリア膜
48…層間絶縁膜
50a、50b…コンタクトホール
52a、52b…コンタクトホール
54a、54b…導体プラグ
56…第1金属配線層
56a、56b、56c…配線
58…バリア膜
60…シリコン酸化膜
61…シリコン酸化膜
62…バリア膜
64…シリコン酸化膜
66…層間絶縁膜
68…コンタクトホール
70…導体プラグ
72…第2金属配線層
72a、72b…配線
74…シリコン酸化膜
76…シリコン酸化膜
78…バリア膜
80…シリコン酸化膜
82…層間絶縁膜
84a、84b…コンタクトホール
86a、86b…導体プラグ
88…第3金属配線層
88a、88b…配線
90…シリコン酸化膜
92…シリコン窒化膜
94…ポリイミド樹脂膜
96…開口部
96a…開口部
96b…開口部
98…フォトレジスト膜
100…フォトレジスト膜
102…フォトレジスト膜
Claims (10)
- 半導体基板上に、下部電極と、前記下部電極上に形成された強誘電体膜と、前記強誘電体膜上に形成された上部電極とを有する強誘電体キャパシタを形成する工程と、
前記半導体基板上及び前記強誘電体キャパシタ上に、第1の絶縁膜を形成する工程と、
前記第1の絶縁膜上に第1の配線を形成する工程と、
前記第1の絶縁膜上及び前記第1の配線上に、第2の絶縁膜を形成する工程と、
前記第2の絶縁膜の表面を平坦化する工程と、
熱処理炉を用いて熱処理を行うことにより、前記第2の絶縁膜中から水分を除去する工程と、
N2Oガス又はN2ガスを用いて生成されたプラズマ雰囲気中にて熱処理を行うことにより、前記第2の絶縁膜中から水分を除去するとともに、前記第2の絶縁膜の表面を窒化する工程と、
前記第2の絶縁膜上に、水素又は水分の拡散を防止する平坦な第1のバリア膜を形成する工程と、
前記第1のバリア膜及び前記第2の絶縁膜に、前記第1の配線に達する第1のコンタクトホールを形成する工程と、
前記第1のコンタクトホール内に第1の導体プラグを埋め込む工程と
を有することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記熱処理炉を用いて熱処理を行う工程の後に、前記プラズマ雰囲気中にて熱処理を行う
ことを特徴とする半導体装置の製造方法。 - 請求項1又は2記載の半導体装置の製造方法において、
前記導体プラグを埋め込む工程では、タングステンより成る導体プラグをCVD法により埋め込む
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至3のいずれか1項に記載の半導体装置の製造方法において、
前記第1のバリア膜は、酸化アルミニウム、酸化チタン、又は酸化タンタルより成る
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至4のいずれか1項に記載の半導体装置の製造方法において、
前記熱処理炉を用いて熱処理を行う工程では、前記熱処理炉内にN2Oガス又はN2ガスを導入しながら、熱処理を行う
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至5のいずれか1項に記載の半導体装置の製造方法において、
前記熱処理炉を用いて熱処理を行う工程における熱処理温度は、350〜650℃である
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至6のいずれか1項に記載の半導体装置の製造方法において、
前記熱処理炉を用いて熱処理を行う工程における熱処理時間は、30〜120分である
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至7のいずれか1項に記載の半導体装置の製造方法において、
前記プラズマ雰囲気中にて熱処理を行う工程における熱処理温度は、350〜400℃である
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至8のいずれか1項に記載の半導体装置の製造方法において、
前記プラズマ雰囲気中にて熱処理を行う工程における熱処理時間は、2〜4分である
ことを特徴とする半導体装置の製造方法。 - 請求項1乃至9のいずれか1項に記載の半導体装置の製造方法において、
前記第1の導体プラグを埋め込む工程の後に、前記第1のバリア膜上に第2の配線を形成する工程と;前記第1のバリア膜上及び前記第2の配線上に第3の絶縁膜を形成する工程と;前記第3の絶縁膜の表面を平坦化する工程と;熱処理炉を用いて熱処理を行うことにより、前記第3の絶縁膜中から水分を除去する工程と;N2Oガス又はN2ガスを用いて生成されたプラズマ雰囲気中にて熱処理を行うことにより、前記第3の絶縁膜中から水分を除去するとともに、前記第3の絶縁膜の表面を窒化する工程と;前記第3の絶縁膜上に水素又は水分の拡散を防止する平坦な第4のバリア膜を形成する工程と;前記第4のバリア膜及び前記第3の絶縁膜に前記第2の配線に達する第2のコンタクトホールを形成する工程と;前記第2のコンタクトホール内に第2の導体プラグを埋め込む工程とを更に有する
ことを特徴とする半導体装置の製造方法。
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US8552484B2 (en) * | 2004-07-02 | 2013-10-08 | Fujitsu Semiconductor Limited | Semiconductor device and method for fabricating the same |
JP4632843B2 (ja) * | 2005-04-12 | 2011-02-16 | Okiセミコンダクタ株式会社 | 強誘電体メモリ装置及びその製造方法 |
JP2008028229A (ja) * | 2006-07-24 | 2008-02-07 | Seiko Epson Corp | 強誘電体メモリの製造方法 |
KR101100142B1 (ko) * | 2007-02-21 | 2011-12-29 | 후지쯔 세미컨덕터 가부시키가이샤 | 반도체 장치와 그 제조 방법 |
JP5272336B2 (ja) * | 2007-06-21 | 2013-08-28 | 東京エレクトロン株式会社 | 半導体装置の製造方法、プラズマエッチング方法及びプラズマエッチング装置 |
US20110079878A1 (en) * | 2009-10-07 | 2011-04-07 | Texas Instruments Incorporated | Ferroelectric capacitor encapsulated with a hydrogen barrier |
US9018089B2 (en) * | 2011-08-30 | 2015-04-28 | International Business Machines Corporation | Multiple step anneal method and semiconductor formed by multiple step anneal |
US9006584B2 (en) | 2013-08-06 | 2015-04-14 | Texas Instruments Incorporated | High voltage polymer dielectric capacitor isolation device |
US10361213B2 (en) | 2016-06-28 | 2019-07-23 | Sandisk Technologies Llc | Three dimensional memory device containing multilayer wordline barrier films and method of making thereof |
US10355139B2 (en) | 2016-06-28 | 2019-07-16 | Sandisk Technologies Llc | Three-dimensional memory device with amorphous barrier layer and method of making thereof |
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