JP2007096278A5 - - Google Patents

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Publication number
JP2007096278A5
JP2007096278A5 JP2006224310A JP2006224310A JP2007096278A5 JP 2007096278 A5 JP2007096278 A5 JP 2007096278A5 JP 2006224310 A JP2006224310 A JP 2006224310A JP 2006224310 A JP2006224310 A JP 2006224310A JP 2007096278 A5 JP2007096278 A5 JP 2007096278A5
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JP
Japan
Prior art keywords
semiconductor device
layer
stacked
thermosetting resin
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006224310A
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English (en)
Japanese (ja)
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JP2007096278A (ja
JP5116268B2 (ja
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Application filed filed Critical
Priority to JP2006224310A priority Critical patent/JP5116268B2/ja
Priority claimed from JP2006224310A external-priority patent/JP5116268B2/ja
Priority to US11/468,181 priority patent/US20070045788A1/en
Publication of JP2007096278A publication Critical patent/JP2007096278A/ja
Priority to US12/501,939 priority patent/US7863101B2/en
Publication of JP2007096278A5 publication Critical patent/JP2007096278A5/ja
Priority to US12/958,584 priority patent/US20110084405A1/en
Application granted granted Critical
Publication of JP5116268B2 publication Critical patent/JP5116268B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2006224310A 2005-08-31 2006-08-21 積層型半導体装置およびその製造方法 Expired - Fee Related JP5116268B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006224310A JP5116268B2 (ja) 2005-08-31 2006-08-21 積層型半導体装置およびその製造方法
US11/468,181 US20070045788A1 (en) 2005-08-31 2006-08-29 Stacking semiconductor device and production method thereof
US12/501,939 US7863101B2 (en) 2005-08-31 2009-07-13 Stacking semiconductor device and production method thereof
US12/958,584 US20110084405A1 (en) 2005-08-31 2010-12-02 Stacking semiconductor device and production method thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005250511 2005-08-31
JP2005250511 2005-08-31
JP2006224310A JP5116268B2 (ja) 2005-08-31 2006-08-21 積層型半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2007096278A JP2007096278A (ja) 2007-04-12
JP2007096278A5 true JP2007096278A5 (enExample) 2009-09-17
JP5116268B2 JP5116268B2 (ja) 2013-01-09

Family

ID=37802903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006224310A Expired - Fee Related JP5116268B2 (ja) 2005-08-31 2006-08-21 積層型半導体装置およびその製造方法

Country Status (2)

Country Link
US (3) US20070045788A1 (enExample)
JP (1) JP5116268B2 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006324568A (ja) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd 多層モジュールとその製造方法
JP5116268B2 (ja) * 2005-08-31 2013-01-09 キヤノン株式会社 積層型半導体装置およびその製造方法
JP4742844B2 (ja) * 2005-12-15 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8110899B2 (en) * 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US7692946B2 (en) * 2007-06-29 2010-04-06 Intel Corporation Memory array on more than one die
US7619305B2 (en) * 2007-08-15 2009-11-17 Powertech Technology Inc. Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
US8105915B2 (en) * 2009-06-12 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers
JP2011077108A (ja) * 2009-09-29 2011-04-14 Elpida Memory Inc 半導体装置
JP5409427B2 (ja) * 2010-02-17 2014-02-05 キヤノン株式会社 プリント回路板及び半導体装置
JP2012033875A (ja) 2010-06-30 2012-02-16 Canon Inc 積層型半導体装置
KR101712043B1 (ko) * 2010-10-14 2017-03-03 삼성전자주식회사 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법
US8299596B2 (en) * 2010-12-14 2012-10-30 Stats Chippac Ltd. Integrated circuit packaging system with bump conductors and method of manufacture thereof
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9934836B2 (en) * 2011-06-27 2018-04-03 Thin Film Electronics Asa Short circuit reduction in an electronic component comprising a stack of layers arranged on a flexible substrate
KR20130005465A (ko) * 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
TWI546911B (zh) * 2012-12-17 2016-08-21 巨擘科技股份有限公司 封裝結構及封裝方法
US9059241B2 (en) * 2013-01-29 2015-06-16 International Business Machines Corporation 3D assembly for interposer bow
CN104465427B (zh) * 2013-09-13 2018-08-03 日月光半导体制造股份有限公司 封装结构及半导体工艺
CN107109140A (zh) 2014-12-19 2017-08-29 3M创新有限公司 在电子装置中替换油墨阶挡板的粘合剂
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
JP6916471B2 (ja) 2017-01-19 2021-08-11 株式会社村田製作所 電子部品及び電子部品の製造方法
US9947634B1 (en) * 2017-06-13 2018-04-17 Northrop Grumman Systems Corporation Robust mezzanine BGA connector
CN110634806A (zh) * 2018-06-21 2019-12-31 美光科技公司 半导体装置组合件和其制造方法
US11282716B2 (en) * 2019-11-08 2022-03-22 International Business Machines Corporation Integration structure and planar joining
CN113053833A (zh) * 2019-12-26 2021-06-29 财团法人工业技术研究院 一种半导体装置及其制作方法
US11502056B2 (en) * 2020-07-08 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure in semiconductor package and manufacturing method thereof

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2944449B2 (ja) * 1995-02-24 1999-09-06 日本電気株式会社 半導体パッケージとその製造方法
JP2806357B2 (ja) * 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
JPH10294423A (ja) * 1997-04-17 1998-11-04 Nec Corp 半導体装置
US6104093A (en) * 1997-04-24 2000-08-15 International Business Machines Corporation Thermally enhanced and mechanically balanced flip chip package and method of forming
JPH11204679A (ja) * 1998-01-08 1999-07-30 Mitsubishi Electric Corp 半導体装置
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
US6274929B1 (en) * 1998-09-01 2001-08-14 Texas Instruments Incorporated Stacked double sided integrated circuit package
JP3147087B2 (ja) * 1998-06-17 2001-03-19 日本電気株式会社 積層型半導体装置放熱構造
US5854507A (en) * 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6316289B1 (en) * 1998-11-12 2001-11-13 Amerasia International Technology Inc. Method of forming fine-pitch interconnections employing a standoff mask
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
JP3722209B2 (ja) * 2000-09-05 2005-11-30 セイコーエプソン株式会社 半導体装置
JP4023159B2 (ja) * 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
JP2003318361A (ja) * 2002-04-19 2003-11-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2004281818A (ja) * 2003-03-17 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法
JP2004281919A (ja) 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4096774B2 (ja) * 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
JP3786103B2 (ja) * 2003-05-02 2006-06-14 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US7173325B2 (en) * 2003-08-29 2007-02-06 C-Core Technologies, Inc. Expansion constrained die stack
US7180165B2 (en) * 2003-09-05 2007-02-20 Sanmina, Sci Corporation Stackable electronic assembly
KR100585226B1 (ko) * 2004-03-10 2006-06-01 삼성전자주식회사 방열판을 갖는 반도체 패키지 및 그를 이용한 적층 패키지
JP2006114604A (ja) * 2004-10-13 2006-04-27 Toshiba Corp 半導体装置及びその組立方法
JP5116268B2 (ja) * 2005-08-31 2013-01-09 キヤノン株式会社 積層型半導体装置およびその製造方法
JP4719009B2 (ja) * 2006-01-13 2011-07-06 ルネサスエレクトロニクス株式会社 基板および半導体装置
JP2007266111A (ja) * 2006-03-27 2007-10-11 Sharp Corp 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法
JP5075463B2 (ja) * 2007-04-19 2012-11-21 ルネサスエレクトロニクス株式会社 半導体装置
US20090039490A1 (en) * 2007-08-08 2009-02-12 Powertech Technology Inc. Mounting assembly of semiconductor packages prevent soldering defects caused by substrate warpage

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