JP2007005536A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2007005536A
JP2007005536A JP2005183264A JP2005183264A JP2007005536A JP 2007005536 A JP2007005536 A JP 2007005536A JP 2005183264 A JP2005183264 A JP 2005183264A JP 2005183264 A JP2005183264 A JP 2005183264A JP 2007005536 A JP2007005536 A JP 2007005536A
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Japan
Prior art keywords
film
dummy pattern
dielectric constant
low dielectric
pattern
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Pending
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JP2005183264A
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English (en)
Japanese (ja)
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JP2007005536A5 (enExample
Inventor
Kazuro Tomita
和朗 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005183264A priority Critical patent/JP2007005536A/ja
Priority to US11/455,699 priority patent/US7420278B2/en
Publication of JP2007005536A publication Critical patent/JP2007005536A/ja
Publication of JP2007005536A5 publication Critical patent/JP2007005536A5/ja
Priority to US12/186,973 priority patent/US20080296777A1/en
Priority to US12/461,134 priority patent/US7843066B2/en
Priority to US12/884,256 priority patent/US8004086B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/0105—Tin [Sn]
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    • H01L2924/01073—Tantalum [Ta]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2005183264A 2005-06-23 2005-06-23 半導体装置 Pending JP2007005536A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2005183264A JP2007005536A (ja) 2005-06-23 2005-06-23 半導体装置
US11/455,699 US7420278B2 (en) 2005-06-23 2006-06-20 Semiconductor device
US12/186,973 US20080296777A1 (en) 2005-06-23 2008-08-06 Semiconductor device
US12/461,134 US7843066B2 (en) 2005-06-23 2009-08-03 Semiconductor device
US12/884,256 US8004086B2 (en) 2005-06-23 2010-09-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005183264A JP2007005536A (ja) 2005-06-23 2005-06-23 半導体装置

Publications (2)

Publication Number Publication Date
JP2007005536A true JP2007005536A (ja) 2007-01-11
JP2007005536A5 JP2007005536A5 (enExample) 2008-07-10

Family

ID=37566364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005183264A Pending JP2007005536A (ja) 2005-06-23 2005-06-23 半導体装置

Country Status (2)

Country Link
US (4) US7420278B2 (enExample)
JP (1) JP2007005536A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009164329A (ja) * 2008-01-07 2009-07-23 Panasonic Corp 半導体装置
JP2009290090A (ja) * 2008-05-30 2009-12-10 Renesas Technology Corp 半導体装置およびその製造方法
JP2013225709A (ja) * 2013-07-29 2013-10-31 Renesas Electronics Corp 半導体装置およびその製造方法
JP2016063218A (ja) * 2014-09-19 2016-04-25 インテル コーポレイション 相互接続ルーティング構成及び関連技術

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006046182B4 (de) * 2006-09-29 2010-11-11 Infineon Technologies Ag Halbleiterelement mit einer Stützstruktur sowie Herstellungsverfahren
US9466579B2 (en) * 2007-07-26 2016-10-11 Nxp B.V. Reinforced structure for a stack of layers in a semiconductor component
US8476629B2 (en) * 2011-09-27 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced wafer test line structure
US8796855B2 (en) 2012-01-13 2014-08-05 Freescale Semiconductor, Inc. Semiconductor devices with nonconductive vias
US9041204B2 (en) * 2012-03-30 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad structure with dense via array
JP5968711B2 (ja) * 2012-07-25 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9620460B2 (en) 2014-07-02 2017-04-11 Samsung Electronics Co., Ltd. Semiconductor chip, semiconductor package and fabricating method thereof
KR102272214B1 (ko) * 2015-01-14 2021-07-02 삼성디스플레이 주식회사 표시 장치
KR102019355B1 (ko) 2017-11-01 2019-09-09 삼성전자주식회사 반도체 패키지
JP7085417B2 (ja) * 2018-06-25 2022-06-16 ルネサスエレクトロニクス株式会社 半導体装置
KR102807501B1 (ko) * 2019-10-02 2025-05-16 삼성전자주식회사 두꺼운 금속층을 갖는 반도체 소자들
JP2021082703A (ja) 2019-11-19 2021-05-27 キオクシア株式会社 半導体装置およびその製造方法
KR102858393B1 (ko) * 2021-02-18 2025-09-11 삼성디스플레이 주식회사 표시 장치

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247664A (ja) * 1997-03-04 1998-09-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2000150521A (ja) * 1998-11-13 2000-05-30 Motorola Inc 集積回路
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
JP2001217248A (ja) * 2000-02-04 2001-08-10 Nec Corp 半導体装置の配線形成方法
JP2003218114A (ja) * 2002-01-22 2003-07-31 Toshiba Corp 半導体装置及びその製造方法
JP2003273221A (ja) * 2002-03-15 2003-09-26 Fujitsu Ltd 配線の遅延調整を可能にする集積回路のレイアウト方法及びそのプログラム
JP2005085939A (ja) * 2003-09-08 2005-03-31 Renesas Technology Corp 半導体装置およびその製造方法
JP2005123587A (ja) * 2003-09-26 2005-05-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2006024698A (ja) * 2004-07-07 2006-01-26 Toshiba Corp 半導体装置及びその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267323A (ja) 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6908841B2 (en) * 2002-09-20 2005-06-21 Infineon Technologies Ag Support structures for wirebond regions of contact pads over low modulus materials

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247664A (ja) * 1997-03-04 1998-09-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2000150521A (ja) * 1998-11-13 2000-05-30 Motorola Inc 集積回路
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
JP2001217248A (ja) * 2000-02-04 2001-08-10 Nec Corp 半導体装置の配線形成方法
JP2003218114A (ja) * 2002-01-22 2003-07-31 Toshiba Corp 半導体装置及びその製造方法
JP2003273221A (ja) * 2002-03-15 2003-09-26 Fujitsu Ltd 配線の遅延調整を可能にする集積回路のレイアウト方法及びそのプログラム
JP2005085939A (ja) * 2003-09-08 2005-03-31 Renesas Technology Corp 半導体装置およびその製造方法
JP2005123587A (ja) * 2003-09-26 2005-05-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2006024698A (ja) * 2004-07-07 2006-01-26 Toshiba Corp 半導体装置及びその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009164329A (ja) * 2008-01-07 2009-07-23 Panasonic Corp 半導体装置
JP2009290090A (ja) * 2008-05-30 2009-12-10 Renesas Technology Corp 半導体装置およびその製造方法
US8829679B2 (en) 2008-05-30 2014-09-09 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
JP2013225709A (ja) * 2013-07-29 2013-10-31 Renesas Electronics Corp 半導体装置およびその製造方法
JP2016063218A (ja) * 2014-09-19 2016-04-25 インテル コーポレイション 相互接続ルーティング構成及び関連技術

Also Published As

Publication number Publication date
US8004086B2 (en) 2011-08-23
US20110001242A1 (en) 2011-01-06
US7843066B2 (en) 2010-11-30
US20060289997A1 (en) 2006-12-28
US20090289373A1 (en) 2009-11-26
US20080296777A1 (en) 2008-12-04
US7420278B2 (en) 2008-09-02

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