JP2006516824A - ウエハ・スクライブ領域の金属低減 - Google Patents

ウエハ・スクライブ領域の金属低減 Download PDF

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Publication number
JP2006516824A
JP2006516824A JP2006502974A JP2006502974A JP2006516824A JP 2006516824 A JP2006516824 A JP 2006516824A JP 2006502974 A JP2006502974 A JP 2006502974A JP 2006502974 A JP2006502974 A JP 2006502974A JP 2006516824 A JP2006516824 A JP 2006516824A
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JP
Japan
Prior art keywords
wafer
metal
layer
saw
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2006502974A
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English (en)
Japanese (ja)
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JP2006516824A5 (enExample
Inventor
ケー． ポズダー、スコット
エス． ユーリン、トレント
エヌ． ラマナサン、ラクシュミ
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NXP USA Inc
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NXP USA Inc
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Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2006516824A publication Critical patent/JP2006516824A/ja
Publication of JP2006516824A5 publication Critical patent/JP2006516824A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
JP2006502974A 2003-01-27 2004-01-23 ウエハ・スクライブ領域の金属低減 Pending JP2006516824A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/351,798 US6951801B2 (en) 2003-01-27 2003-01-27 Metal reduction in wafer scribe area
PCT/US2004/001925 WO2004073014A2 (en) 2003-01-27 2004-01-23 Metal reduction in wafer scribe area

Publications (2)

Publication Number Publication Date
JP2006516824A true JP2006516824A (ja) 2006-07-06
JP2006516824A5 JP2006516824A5 (enExample) 2007-03-08

Family

ID=32735850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006502974A Pending JP2006516824A (ja) 2003-01-27 2004-01-23 ウエハ・スクライブ領域の金属低減

Country Status (6)

Country Link
US (1) US6951801B2 (enExample)
JP (1) JP2006516824A (enExample)
KR (1) KR101001530B1 (enExample)
CN (1) CN1777978B (enExample)
TW (1) TWI325155B (enExample)
WO (1) WO2004073014A2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008066716A (ja) * 2006-08-10 2008-03-21 Matsushita Electric Ind Co Ltd 半導体装置
JP2009141074A (ja) * 2007-12-05 2009-06-25 Elpida Memory Inc 半導体ウエハ及びその製造方法
JP2011124277A (ja) * 2009-12-08 2011-06-23 Shinko Electric Ind Co Ltd 電子装置の切断方法
JP2020202336A (ja) * 2019-06-13 2020-12-17 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． ウェーハダイシング方法およびダイ

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232448A1 (en) * 2003-05-23 2004-11-25 Taiwan Semiconductor Manufacturing Co. Layout style in the interface between input/output (I/O) cell and bond pad
CN100370580C (zh) * 2004-03-29 2008-02-20 雅马哈株式会社 半导体晶片及其制造方法
US7553700B2 (en) * 2004-05-11 2009-06-30 Gem Services, Inc. Chemical-enhanced package singulation process
US7223673B2 (en) * 2004-07-15 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device with crack prevention ring
JP4288229B2 (ja) * 2004-12-24 2009-07-01 パナソニック株式会社 半導体チップの製造方法
JP4471852B2 (ja) * 2005-01-21 2010-06-02 パナソニック株式会社 半導体ウェハ及びそれを用いた製造方法ならびに半導体装置
US7572738B2 (en) * 2005-05-23 2009-08-11 Sony Corporation Crack stop trenches in multi-layered low-k semiconductor devices
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
KR100672728B1 (ko) * 2005-07-12 2007-01-22 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7250670B2 (en) * 2005-09-27 2007-07-31 United Microelectronics Corp. Semiconductor structure and fabricating method thereof
CN100481455C (zh) * 2005-12-22 2009-04-22 中芯国际集成电路制造(上海)有限公司 具有不全接触通孔栈的密封环结构
US7511379B1 (en) * 2006-03-23 2009-03-31 National Semiconductor Corporation Surface mountable direct chip attach device and method including integral integrated circuit
US7732897B2 (en) * 2006-06-15 2010-06-08 Taiwan Semiconductor Manufacturing Co., Ltd Methods of die sawing and structures formed thereby
US7679195B2 (en) * 2006-06-20 2010-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. PAD structure and method of testing
US7622364B2 (en) * 2006-08-18 2009-11-24 International Business Machines Corporation Bond pad for wafer and package for CMOS imager
US7566915B2 (en) * 2006-12-29 2009-07-28 Intel Corporation Guard ring extension to prevent reliability failures
US9601443B2 (en) * 2007-02-13 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Test structure for seal ring quality monitor
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US7674689B2 (en) * 2007-09-20 2010-03-09 Infineon Technologies Ag Method of making an integrated circuit including singulating a semiconductor wafer
KR20090046993A (ko) * 2007-11-07 2009-05-12 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
US8013425B2 (en) * 2008-05-13 2011-09-06 United Microelectronics Corp. Scribe line structure for wafer dicing and method of making the same
US7821104B2 (en) * 2008-08-29 2010-10-26 Freescale Semiconductor, Inc. Package device having crack arrest feature and method of forming
US8022509B2 (en) * 2008-11-28 2011-09-20 United Microelectronics Corp. Crack stopping structure and method for fabricating the same
WO2010086952A1 (ja) * 2009-01-30 2010-08-05 パナソニック株式会社 半導体装置及びその製造方法
US8237246B2 (en) * 2009-02-12 2012-08-07 International Business Machines Corporation Deep trench crackstops under contacts
US8748295B2 (en) 2009-06-15 2014-06-10 Infineon Technologies Ag Pads with different width in a scribe line region and method for manufacturing these pads
JP5175803B2 (ja) * 2009-07-01 2013-04-03 新光電気工業株式会社 半導体装置の製造方法
US8357996B2 (en) * 2009-11-17 2013-01-22 Cree, Inc. Devices with crack stops
JP2011134824A (ja) * 2009-12-24 2011-07-07 Elpida Memory Inc 半導体ウエハ、半導体ウエハの製造方法、および半導体装置
JP2011199123A (ja) * 2010-03-23 2011-10-06 Elpida Memory Inc 半導体装置およびその製造方法
US8531008B2 (en) * 2010-11-23 2013-09-10 Infineon Technologies Ag Material structure in scribe line and method of separating chips
US9331019B2 (en) 2012-11-29 2016-05-03 Infineon Technologies Ag Device comprising a ductile layer and method of making the same
US8659173B1 (en) * 2013-01-04 2014-02-25 International Business Machines Corporation Isolated wire structures with reduced stress, methods of manufacturing and design structures
US8937009B2 (en) 2013-04-25 2015-01-20 International Business Machines Corporation Far back end of the line metallization method and structures
US9490173B2 (en) * 2013-10-30 2016-11-08 Infineon Technologies Ag Method for processing wafer
CN104701271A (zh) * 2013-12-05 2015-06-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10553508B2 (en) 2014-01-13 2020-02-04 Nxp Usa, Inc. Semiconductor manufacturing using disposable test circuitry within scribe lanes
CN105025480B (zh) * 2014-04-29 2019-04-05 中国电信股份有限公司 用户卡数字签名验证的方法与系统
US9601354B2 (en) 2014-08-27 2017-03-21 Nxp Usa, Inc. Semiconductor manufacturing for forming bond pads and seal rings
JP6571344B2 (ja) * 2015-02-19 2019-09-04 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置
DE102017123846B4 (de) * 2017-10-13 2020-03-12 Infineon Technologies Austria Ag Leistungshalbleiter-Die und Halbleiterwafer umfassend einen Oxid-Peeling Stopper und Verfahren zum Verarbeiten eines Halbleiterwafers
US10734304B2 (en) 2018-11-16 2020-08-04 Texas Instruments Incorporated Plating for thermal management
CN111785686B (zh) * 2019-04-03 2023-08-15 华邦电子股份有限公司 切割晶圆的方法及晶粒

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246647A (ja) * 1984-05-22 1985-12-06 Nec Corp 半導体装置
JPH05326697A (ja) * 1992-05-23 1993-12-10 Sony Corp 半導体装置の製造方法
JPH06232256A (ja) * 1992-12-29 1994-08-19 Internatl Business Mach Corp <Ibm> 半導体デバイスのクラックストップ形成方法及び半導体デバイス
JPH0883888A (ja) * 1994-09-06 1996-03-26 Internatl Business Mach Corp <Ibm> 集積回路チップ、集積回路チップの形成方法、電子モジュール、および電子モジュールの形成方法
JPH08162456A (ja) * 1994-12-07 1996-06-21 Kawasaki Steel Corp バンプの製造方法
JPH08213402A (ja) * 1995-02-03 1996-08-20 Casio Comput Co Ltd 半導体装置の製造方法
JPH09306913A (ja) * 1996-05-15 1997-11-28 Citizen Watch Co Ltd 半導体装置およびその製造方法
JPH10154670A (ja) * 1996-11-26 1998-06-09 Toshiba Corp 半導体装置の製造方法
JPH11204525A (ja) * 1998-01-14 1999-07-30 Seiko Epson Corp 半導体装置の製造方法
JP2000252236A (ja) * 1999-03-03 2000-09-14 Toshiba Corp 半導体装置及びその製造方法
JP2002217196A (ja) * 2001-01-17 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136354A (en) * 1989-04-13 1992-08-04 Seiko Epson Corporation Semiconductor device wafer with interlayer insulating film covering the scribe lines
US5789302A (en) * 1997-03-24 1998-08-04 Siemens Aktiengesellschaft Crack stops
US6075280A (en) * 1997-12-31 2000-06-13 Winbond Electronics Corporation Precision breaking of semiconductor wafer into chips by applying an etch process
CN1138305C (zh) * 1999-05-27 2004-02-11 国际商业机器公司 含有导电熔丝的半导体结构及其制造方法
US6362524B1 (en) 2000-07-26 2002-03-26 Advanced Micro Devices, Inc. Edge seal ring for copper damascene process and method for fabrication thereof
US6784556B2 (en) * 2002-04-19 2004-08-31 Kulicke & Soffa Investments, Inc. Design of interconnection pads with separated probing and wire bonding regions
KR100598245B1 (ko) 2002-12-30 2006-07-07 동부일렉트로닉스 주식회사 반도체 금속 배선 형성 방법
US6881610B2 (en) * 2003-01-02 2005-04-19 Intel Corporation Method and apparatus for preparing a plurality of dice in wafers

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246647A (ja) * 1984-05-22 1985-12-06 Nec Corp 半導体装置
JPH05326697A (ja) * 1992-05-23 1993-12-10 Sony Corp 半導体装置の製造方法
JPH06232256A (ja) * 1992-12-29 1994-08-19 Internatl Business Mach Corp <Ibm> 半導体デバイスのクラックストップ形成方法及び半導体デバイス
JPH0883888A (ja) * 1994-09-06 1996-03-26 Internatl Business Mach Corp <Ibm> 集積回路チップ、集積回路チップの形成方法、電子モジュール、および電子モジュールの形成方法
JPH08162456A (ja) * 1994-12-07 1996-06-21 Kawasaki Steel Corp バンプの製造方法
JPH08213402A (ja) * 1995-02-03 1996-08-20 Casio Comput Co Ltd 半導体装置の製造方法
JPH09306913A (ja) * 1996-05-15 1997-11-28 Citizen Watch Co Ltd 半導体装置およびその製造方法
JPH10154670A (ja) * 1996-11-26 1998-06-09 Toshiba Corp 半導体装置の製造方法
JPH11204525A (ja) * 1998-01-14 1999-07-30 Seiko Epson Corp 半導体装置の製造方法
JP2000252236A (ja) * 1999-03-03 2000-09-14 Toshiba Corp 半導体装置及びその製造方法
JP2002217196A (ja) * 2001-01-17 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008066716A (ja) * 2006-08-10 2008-03-21 Matsushita Electric Ind Co Ltd 半導体装置
JP2009141074A (ja) * 2007-12-05 2009-06-25 Elpida Memory Inc 半導体ウエハ及びその製造方法
US7977232B2 (en) 2007-12-05 2011-07-12 Elpida Memory, Inc. Semiconductor wafer including cracking stopper structure and method of forming the same
JP2011124277A (ja) * 2009-12-08 2011-06-23 Shinko Electric Ind Co Ltd 電子装置の切断方法
JP2020202336A (ja) * 2019-06-13 2020-12-17 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． ウェーハダイシング方法およびダイ

Also Published As

Publication number Publication date
CN1777978A (zh) 2006-05-24
KR101001530B1 (ko) 2010-12-16
WO2004073014A2 (en) 2004-08-26
CN1777978B (zh) 2010-07-21
US20040147097A1 (en) 2004-07-29
TW200416857A (en) 2004-09-01
US6951801B2 (en) 2005-10-04
WO2004073014A3 (en) 2005-04-21
KR20050095630A (ko) 2005-09-29
TWI325155B (en) 2010-05-21

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