CN101685794B - 使用绝缘膜保护半导体芯片的侧壁 - Google Patents
使用绝缘膜保护半导体芯片的侧壁 Download PDFInfo
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Abstract
一种形成集成电路结构的方法,包括:提供晶片,所述晶片具有第一半导体芯片、第二半导体芯片、以及在第一半导体芯片和第二半导体芯片之间并且与两者邻接的切割槽;在切割槽中形成凹槽,其中,凹槽的底部不高于晶片中半导体衬底的顶面;在晶片之上形成第一绝缘膜,其中,第一绝缘膜延伸至凹槽;将第一绝缘膜的一部分从凹槽的中心移除,其中,第一绝缘膜的剩余部分包括凹槽中的边缘;以及切开晶片,使得第一半导体芯片和第二半导体芯片分离。
Description
技术领域
本发明整体涉及集成电路形成处理,特别涉及防止集成电路和互连结构遭到腐蚀和剥离。
背景技术
在典型的集成电路形成处理中,首先制造每个均包括多个相同半导体芯片的半导体晶片。制造之后,半导体晶片被切开,以使得半导体芯片分离,这样每个半导体芯片均可以被单独封装。
在半导体晶片上,切割槽(scribe line)被设置在半导体芯片之间。切割槽可以独立于集成电路,或者具有在其中形成的测试电路,其中,测试电路可以被牺牲而不影响半导体芯片的功能。
典型地,形成密封环,以防止半导体芯片中的集成电路受潮和污染。然而,对于封装过程来说,需要执行一些后端处理用于形成接合焊盘和/或安装焊锡球。这些处理包括形成保护层(模塑料),形成重新分布槽(redistribution line),以及形成接合焊盘。因此,产生了各种材料层和相应界面。这些界面没有被适当地保护,并且一些界面可能在用于分离半导体芯片的晶片切割处理后暴露于外部环境。结果,水分可能渗入这些界面并且腐蚀半导体芯片中的铜线。另外,由于铜线的形成通常包括氟,铜线的腐蚀进一步导致氟被释放。氟具有加速水分腐蚀铝焊盘的效果。而且,界面的暴露可能进一步导致保护层的剥离。上述问题中的任一项都可能导致电路性能的降低,或电路故障。因此,需要一种新的集成方法来防止界面遭到水分渗入。
发明内容
根据本发明的一个方面,一种形成集成电路结构的方法包括:提供晶片,该晶片具有第一半导体芯片、第二半导体芯片、以及在第一半导体芯片和第二半导体芯片之间并且与两者邻接的切割槽;在切割槽中形成凹槽;以及在晶片之上形成绝缘膜,并且将绝缘膜的一部分从凹槽的中心移除。绝缘膜延伸至凹槽中。凹槽的底部不高于晶片中的半导体衬底的顶面。绝缘膜的剩余部分包括凹槽中的边缘。该方法进一步包括:切开晶片,以使第一半导体芯片和第二半导体芯片分离。
根据本发明的另一个方面,一种形成集成电路结构的方法包括提供具有半导体衬底的晶片。该晶片包括在半导体衬底之上的互连结构;第一半导体芯片,包括半导体衬底的第一部分和互连结构的第一部分;第二半导体芯片,包括半导体衬底的第二部分和互连结构的第二部分;以及切割槽,在第一半导体芯片和第二半导体芯片之间并且与两者邻接。该方法进一步包括在切割槽中形成凹槽。凹槽从晶片的顶面延伸至半导体衬底的顶面之下,并且基本上从切割槽的一端延伸至对端。该方法进一步包括:在晶片之上形成第一绝缘膜,第一绝缘膜延伸至凹槽内;图案化第一绝缘膜,以将第一绝缘膜的一部分从凹槽的中心移除,第一绝缘膜的剩余部分包括凹槽中的第一边缘;在第一绝缘膜之上形成第二绝缘膜,第二绝缘膜延伸至凹槽内;图案化第二绝缘膜,以将第二绝缘膜的一部分从凹槽的中心移除,第二绝缘膜的剩余部分包括凹槽中的第二边缘;以及切开晶片,以使第一半导体芯片和第二半导体芯片分离。
根据本发明的又另一方面,一种形成集成电路结构的方法包括提供晶片。该晶片具有第一半导体芯片、第二半导体芯片、以及在第一半导体芯片和第二半导体芯片之间并且与两者邻接的切割槽。该方法进一步包括在切割槽中形成凹槽,其中,凹槽从晶片的顶面延伸至晶片中的半导体衬底,并且其中,凹槽基本上从切割槽的一端延伸至对端。该方法进一步包括在晶片之上形成绝缘膜。绝缘膜延伸至凹槽。凹槽中的绝缘膜的一部分的顶面比直接在第一芯片之上的绝缘膜的一部分的顶面低。该方法进一步包括图案化绝缘膜,以将绝缘膜的一部分从凹槽的中心移除;以及切开晶片,使得第一半导体芯片和第二半导体芯片分离。
根据本发明的再另一方面,一种集成电路结构包括晶片,该晶片具有第一半导体芯片、第二半导体芯片、以及在第一半导体芯片和第二半导体芯片之间并且与两者邻接的切割槽。该集成电路结构进一步包括在切割槽中并且从晶片的顶面延伸至晶片内的凹槽,其中,凹槽的底部不高于晶片中的半导体衬底的顶面;以及晶片之上的绝缘膜。该缘膜具有覆盖第一半导体芯片并且延伸至凹槽的第一部分。绝缘膜的第一部分具有凹槽内的第一边缘。
根据本发明的还有的另一方面,一种集成电路结构包括半导体芯片和半导体芯片中的半导体衬底。半导体衬底具有边缘。该集成电路结构进一步包括:半导体衬底之上的互连结构;以及在半导体芯片的边缘上并且从边缘的一端延伸至对端的凹槽。半导体衬底的边缘是半导体芯片的边缘的下部。凹槽的底部比半导体衬底的顶面低。该集成电路结构进一步包括在互连结构之上并且延伸至凹槽内的绝缘膜。凹槽内的绝缘膜的边缘基本上平行于半导体衬底的边缘并且与半导体衬底的边缘水平分离。
根据本发明的再另一方面,一种集成电路结构包括半导体芯片和半导体芯片中的半导体衬底。该半导体衬底具有边缘。该集成电路结构进一步包括在半导体衬底之上的互连结构;以及在半导体芯片的边缘上并且从边缘的一端延伸至对端的凹槽。半导体衬底的边缘是半导体芯片的边缘的一部分。凹槽延伸至半导体衬底内。该集成电路结构进一步包括在半导体衬底之上并且延伸至凹槽内的绝缘膜。绝缘膜的顶面包括直接在凹槽之上的第一部分和凹槽外部的第二部分。第一部分比所述第二部分低。
本发明的优点包括对半导体芯片的界面的改进保护。
附图说明
为了更全面地理解本发明及其优点,现在结合附图作为参考进行以下描述,其中:
图1至图16是本发明实施例的制造中的中间阶段的截面图。
具体实施方式
下面,详细描述当前优选实施例的制造和使用。然而,应该认识到,本发明提供了可以在多种特定环境中被具体化的很多可用发明思想。在此所述的特定实施例仅是制造和使用本发明的特定方式的举例说明,而并不限制本发明的范围。
提供了一种新的晶片级芯片规模封装及形成其的方法。阐述了制造本发明的优选实施例的中间阶段。而且论述了各种优选实施例。在本发明的各种视图和说明性实例中,使用类似的参考数字表明类似的元件。
图1示出包括多个半导体芯片的晶片10。为了简单起见,仅示出了两个芯片12和14部分。晶片10包括半导体衬底20和之上的互连结构22。半导体衬底20可以由硅或者其他普遍使用的半导体材料(如锗硅等)组成。集成电路装置(诸如晶体管、电容、电阻(未示出)等)可以形成在半导体衬底20的表面上。如本领域技术人员所熟知的,互连结构22可以包括中间层电介质(ILD)(未示出)、ILD中的插塞接触(未示出)、金属间电介质(IMD)、以及IMD中的金属线和通孔(未示出)。钝化层24可以被形成为互连结构22的顶部,并且可以包括氧化硅上的氮化硅等。焊盘28暴露通过钝化层24,并且可以被电连接到半导体衬底20上的集成电路。焊盘28可以由铝、铜、银、钨、或者其结合形成。
在芯片之间形成切割槽。例如,切割槽16形成在芯片12和14之间,并且被限制于密封环22之间,密封环22是芯片12和14的一部分。如本领域技术人员所熟知的,密封环22由接近芯片参数的互连金属线和通孔形成,其中,密封环22可以形成闭合回路。切割槽16中是测试电路(未示出)和用于将测试电路连接到测试设备的探针的测试焊盘(例如,测试焊盘26)。
参考图2、图3A和图3B,凹槽30形成在切割槽16中并且在晶片10的前表面上。在第一实施例中,如图2和图3A所示,凹槽30使用刀片32形成。刀片32可以具有倾斜边缘。因此,凹槽30也具有倾斜边缘34,其中,倾角α可以小于大约80度,这取决于刀片32的形状。在第二实施例中,如图3B所示,凹槽30使用激光器形成。因此,凹槽30的侧壁34是基本垂直的。凹槽30优选地延伸至半导体衬底20内一段深度D,例如,在大约10μm和大约20μm之间,但是比深度D更大或更小也可以使用。在使用激光器形成凹槽30的实施例中,可以控制处理,使得凹槽30停止在半导体衬底20和互连结构22之间的界面处,或者换句话说,使得深度D等于0μm。应注意到,在俯视图中,晶片10具有多个切割槽16,通常形成具有彼此平行的第一多个切割槽(未示出)以及彼此平行的第二多个切割槽(未示出)的网格,并且第一多个切割槽垂直于第二切割槽。凹槽(一个或多个)30形成在第一和第二多个切割槽中的每个中,因此也形成网格。换句话说,晶片中的所有切割槽都可以形成凹槽。尤其,在第一多个切割槽和第二多个切割槽中的每个中,凹槽优选地基本上从各个切割槽的一端延伸至对端。
图4和图5示出绝缘膜40的形成、固化和图案化。绝缘膜40可以由聚苯并噁唑(polybenzoxazole,PBO)树脂、或者其他具有良好防潮性和强粘着性的有机材料或无机材料形成。在图4中,绝缘膜40被垫带(blanket)涂布,然后被固化,例如,使用热固化。在图5中,执行图案化以使焊盘28暴露。在优选实施例中,凹槽30中的绝缘膜40的中心部分被移除。在可选实施例中,凹槽30中的绝缘膜40部分不被移除。优选地,绝缘膜40的剩余部分覆盖半导体衬底20和互连结构22之间的界面,其中,实线和虚线示出边界42的可能位置。如果俯视,边界42将平行于切割槽16的纵向方向。请注意,绝缘膜40是相对保形的,而且直接在凹槽30之上(换句话说,在凹槽的范围内)的顶面43的部分431比直接在芯片12和14之上的部分432低。
图6示出了重新分布槽44的形成和图案化,也称作后护层互连(Post-Passivation interconnects,PPI)44或滑槽(runner)44。在一个实施例中,重新分布槽44的形成包括喷涂或电镀以形成金属层,例如,包括铝或其他金属合金,以及图案化金属层。在可选实施例中,重新分布槽44通过选择性电镀形成。重新分布槽44被电连接到焊盘28。
图7、图8A和图8B示出了绝缘膜50的形成、固化和图案化。绝缘膜50也可以由聚苯并噁唑(PBO)树脂、或者其他具有良好防潮性和强粘着性的有机材料或无机材料形成。绝缘膜40和50的材料可以是相同的或者不同的。在图7中,绝缘膜50被垫带涂布,然后被固化,例如,使用热固化。在图8A中,执行图案化,使得重新分布槽44的部分暴露。在优选实施例中,凹槽30中的绝缘膜50的中心部分被移除。在可选实施例中,凹槽30中的绝缘膜50的部分不被移除。而且,在优选实施例中,绝缘膜50的剩余部分的边缘52延伸超过绝缘膜40的各个边缘42,因此,绝缘膜40和50之间的界面被隐藏。可选地,如图8B所示,绝缘膜40和50之间的界面被暴露于凹槽30。请注意,绝缘膜50具有顶面53,而且直接在凹槽30之上的顶面53的部分531比直接在芯片12和14之上的部分532低。
参考图9,薄种子层56(也称作凸块底部金属化(Under-BumpMetallurgy,UBM))被垫带形成。种子层56的材料包括铜或铜合金。然而,也可以包括其他材料,如银、金、铝和其结合。在一个实施例中,使用喷涂法形成UBM 56。在其他实施例中,可以使用物理气相沉积(PVD)或电镀。UBM 56的厚度可以小于大约1μm。
图10示出了掩膜58的形成。在优选实施例中,掩膜58是光致抗蚀剂,然而它也可以由其他材料(包括味之素公司生产的薄膜(ABF))组成,如干膜。然后,掩膜58被图案化,并且开口60形成在掩膜58中,使得直接在重新分布槽44之上的UBM 56的部分暴露。
在图11中,开口60选择性地由金属材料填充,在开口60中形成UBM焊盘62。在优选实施例中,填充材料包括铜或铜合金。然而,也可以使用其他材料,如铝、银、金和其结合。形成方法优选包括化学镀,然而还可以使用其他普遍使用的沉积方式,如喷涂、印刷、电镀和化学气相沉积(CVD)方法。在可选实施例中,焊接材料被镀在开口60中,而不是形成UBM焊盘62。
在图12中,掩膜58被移除。结果,位于掩膜58之下的UBM 56部分被暴露。然后,UBM 56的暴露部分通过闪蚀刻被移除。图13中示出所得到的结构。应注意到,UBM 56可能与之上的UBM焊盘62是不可区别的,因为UBM 56可以由与UBM焊盘62类似的材料形成,因此他们呈现成为混合。
接下来,如图14所示,焊锡球66被放置在UBM焊盘的顶部上。在可选实施例中,特征62由焊接材料形成,焊接材料被回流焊(re-flowed),形成焊锡球66。在这种情况下,焊锡球66的下面没有UBM焊盘62。
参考图15,晶片10被切开,使得芯片12和14被分离。在优选实施例中,切口68不接触绝缘膜40和50。这有效地避免了机械应力施加在绝缘膜40和50上,而不利地导致绝缘膜40和50的剥离。因此,半导体衬底20的边缘70基本上分别平行于绝缘膜40和50的边缘42和52,并且与绝缘膜40和50的边缘42和52垂直地不重合。相应地,半导体衬底20的边缘70和绝缘膜50的边缘52(或边缘42)具有非零水平间距S。由于每个芯片12和14均有四个边缘,四个边缘中的每个边缘处都有一个凹槽,因此,芯片12和/或14可以具有一个有四个边的凹口环。即使一个切口68偏离理想路径并且穿过绝缘膜40和50之一,由于芯片有四个边缘,很有可能,芯片的至少一个侧面具有不重合的边缘70和42/52。
图16示出了可选实施例,其中,凹槽30使用激光器形成。因此,凹槽30的侧壁34是垂直的。图16中所示的结构的形成方法和材料与图15中基本相同。
尽管在上述实施例中论述了两个绝缘膜40和50,可以仅形成一个类似于绝缘膜50的绝缘膜。在这种情况下,重新分布槽44直接形成在钝化层24上,而不是形成在绝缘膜40上,并且绝缘膜40的形成被省略。此外,绝缘膜50将延伸至凹槽30内,以覆盖半导体衬底20与之下的互连结构22之间的界面。
图15和16中所示的结构有利地导致绝缘膜40和50的底部向下延伸至半导体衬底20。因此,绝缘膜50和钝化层24之间的传统弱界面免受剥离,并且通过其防止水分渗入芯片12和14。实验结果已经显示,由上述剥离导致的电路降解和故障被基本消除。有利地,本发明的实施例仅仅需要一个附加的凹槽形成处理,而不需要附加的平版印刷步骤和掩膜。
尽管已经详细描述了本发明及其优点,应理解,可以在不脱离如所附权利要求限定的本发明的精神和范围的情况下,进行各种不同的改变,替换和更改。而且,本申请的范围并不限于说明书描述的处理、机械装置、制造、和说明书中描述的问题、手段、方法和步骤的组合的具体实例。本领域的技术人员从本发明的公开将容易地认识到,根据本发明,可以利用处理、机械装置、制造、当前存在的或今后开发的执行与在此所描述的对应实施例中基本相同功能或实现基本相同结果的物质、手段、方法或步骤的结合。因此,附加权利要求应该包括在其范围内的这样的过程、机械装置、制造、物质、手段、方法、或步骤的结合。
Claims (15)
1.一种形成集成电路结构的方法,所述方法包括:
提供晶片,所述晶片包括:
第一半导体芯片;
第二半导体芯片;以及
切割槽,在所述第一半导体芯片和所述第二半导体芯片之间并且与所述第一半导体芯片和所述第二半导体芯片邻接;
在所述切割槽中形成凹槽,其中,所述凹槽的底部不高于所述晶片中的半导体衬底的顶面;
在所述晶片之上形成第一绝缘膜,其中,所述第一绝缘膜延伸至所述凹槽;
将所述第一绝缘膜的一部分从所述凹槽的中心移除,其中,所述第一绝缘膜的剩余部分包括所述凹槽中的边缘;
在所述晶片之上并且在所述第一绝缘膜之下形成第二绝缘膜,其中,所述第二绝缘膜延伸至所述凹槽,将所述第二绝缘膜的一部分从所述凹槽的中心移除,其中,所述第二绝缘膜的剩余部分包括所述凹槽中的边缘;
其中,所述第一绝缘膜的所述边缘向所述切割槽的中心延伸得比所述第二绝缘膜的所述边缘远,以及
切开所述晶片,使得所述第一半导体芯片和所述第二半导体芯片分离。
2.根据权利要求1所述的方法,其中,在所述切开的步骤之后,所述第一绝缘膜的剩余部分的边缘基本上平行于由所述切开的步骤产生的半导体衬底的边缘,并且与所述切开的步骤产生的半导体衬底的边缘垂直地不重合。
3.根据权利要求1所述的方法,其中,
形成所述凹槽的步骤由刀片执行,所述凹槽具有倾斜侧壁;或者
形成所述凹槽的步骤由激光器执行,并且其中,所述凹槽具有基本垂直的侧壁。
4.一种形成集成电路结构的方法,所述方法包括:
提供晶片,所述晶片包括:
半导体衬底;
互连结构,在所述半导体衬底之上;
第一半导体芯片,包括所述半导体衬底的第一部分和所述互连结构的第一部分;
第二半导体芯片,包括所述半导体衬底的第二部分和所述互连结构的第二部分;以及
切割槽,在所述第一半导体芯片和所述第二半导体芯片之间并且与所述第一半导体芯片和所述第二半导体芯片邻接;
在所述切割槽中形成凹槽,其中,所述凹槽从所述晶片的顶面延伸至所述半导体衬底的顶面之下,并且基本从所述切割槽的一端延伸至对端;
在所述晶片之上形成第一绝缘膜,其中,所述第一绝缘膜延伸至所述凹槽;
图案化所述第一绝缘膜,以将所述第一绝缘膜的一部分从所述凹槽的中心移除,其中,所述第一绝缘膜的剩余部分包括所述凹槽中的第一边缘;
在所述第一绝缘膜之上形成第二绝缘膜,其中,所述第二绝缘膜延伸至所述凹槽中;
图案化所述第二绝缘膜,以将所述第二绝缘膜的一部分从所述凹槽的中心移除,其中,所述第二绝缘膜的剩余部分包括所述凹槽中的第二边缘;
其中,所述第二绝缘膜的所述边缘向所述切割槽的中心延伸得比所述第一绝缘膜的所述边缘远,以及
切开所述晶片,使得所述第一半导体芯片和所述第二半导体芯片分离。
5.根据权利要求4所述的方法,进一步包括
形成多个凹槽,每个凹槽均在所述晶片中的多个切割槽中的一个中,并且其中,多个所述凹槽中的每个凹槽均基本从多个所述切割槽中的相应一个切割槽的一端延伸至对端;
在所述第一绝缘膜和所述第二绝缘膜之间形成重新分布槽,在所述晶片的顶面上形成焊锡球,其中,所述焊锡球通过所述第二绝缘膜中的开口电连接至所述重新分布槽。
6.根据权利要求4所述的方法,其中,在所述切开的步骤期间,所述切开的切口水平地位于所述第一半导体芯片和第二半导体芯片的所述第一边缘和所述第二边缘之间并且与所述第一边缘和所述第二边缘分离;
在所述图案化所述第二绝缘膜的步骤之后,所述第二绝缘膜的剩余部分覆盖所述第一绝缘膜的所述第一边缘;以及
在所述图案化所述第二绝缘膜之后,所述第一绝缘膜和所述第二绝缘膜之间的界面被暴露于所述凹槽;
其中,所述形成所述凹槽的步骤由刀片执行,并且其中,所述凹槽具有倾斜侧壁;或者所述形成所述凹槽的步骤由激光器执行,并且其中,所述凹槽具有基本垂直的侧壁。
7.一种形成集成电路结构的方法,所述方法包括:
提供晶片,所述晶片包括:
第一半导体芯片;
第二半导体芯片;以及
切割槽,在所述第一半导体芯片和所述第二半导体芯片之间并且与所述第一半导体芯片和所述第二半导体芯片邻接;
在所述切割槽中形成凹槽,其中,所述凹槽从所述晶片的顶面延伸至所述晶片中的半导体衬底中,并且所述凹槽基本上从所述切割槽的一端延伸至对端;
在所述晶片之上形成第一绝缘膜,其中,所述第一绝缘膜延伸至所述凹槽,并且其中,所述凹槽中的所述第一绝缘膜的一部分的顶面比直接在所述第一芯片之上的所述第一绝缘膜的一部分的顶面低;
图案化所述第一绝缘膜,以将所述第一绝缘膜的一部分从所述凹槽的中心移除;
在所述晶片之上并且在所述第一绝缘膜之下形成第二绝缘膜,其中,所述第二绝缘膜延伸至所述凹槽,将所述第二绝缘膜的一部分从所述凹槽的中心移除,其中,所述第二绝缘膜的剩余部分包括所述凹槽中的边缘;
其中,所述第一绝缘膜的所述边缘向所述切割槽的中心延伸得比所述第二绝缘膜的所述边缘远,以及
切开所述晶片,使得所述第一半导体芯片和所述第二半导体芯片分离。
8.根据权利要求7所述的方法,其中,
在所述图案化所述第一绝缘膜的步骤之后并且所述切开所述晶片的步骤之前,所述第一绝缘膜的剩余部分包括所述凹槽中的边缘;
在所述晶片之上并且在所述第一绝缘膜之下形成第二绝缘膜,其中,所述第二绝缘膜延伸至所述凹槽;
图案化所述第二绝缘膜,以将所述第二绝缘薄膜的一部分从所述凹槽的中心移除,其中,所述第二绝缘膜的剩余部分包括所述凹槽中的边缘;
其中,所述第一绝缘膜的剩余部分的边缘向所述切割槽的中心延伸得比所述第二绝缘膜的剩余部分的边缘远。
9.一种集成电路结构,包括:
晶片,包括:
第一半导体芯片;
第二半导体芯片;以及
切割槽,在所述第一半导体芯片和所述第二半导体芯片之间并且与所述第一半导体芯片和所述第二半导体芯片邻接;
凹槽,在所述切割槽内并且从所述晶片的预面延伸至所述晶片中,其中,所述凹槽的底部不高于所述晶片中的半导体衬底的顶面;以及
第一绝缘膜,在所述晶片之上,其中,所述第一绝缘膜具有覆盖所述第一半导体芯片并延伸至所述凹槽中的第一部分,并且其中,所述第一绝缘膜的所述第一部分具有所述凹槽中的第一边缘;
第二绝缘膜,在所述晶片之上并且在所述第一绝缘膜之下,其中,所述第二绝缘膜包括在所述第一半导体芯片之上的第一部分,并且其中,所述第二绝缘膜的第一部分包括所述凹槽中的第一边缘;
其中,所述第一绝缘膜的第一部分的第一边缘向所述切割槽的中心延伸得比所述第二绝缘膜的第一部分的第一边缘远。
10.根据权利要求9所述的集成电路结构,其中,
所述第一绝缘膜具有覆盖所述第二半导体芯片并延伸至所述凹槽中的第二部分,并且其中,所述第一绝缘膜的第二部分具有所述凹槽中的第二边缘;
所述第一绝缘膜的所述第一部分和所述第二部分彼此在物理上分离,并且其中,所述第一边缘和所述第二边缘彼此分离并且基本上彼此平行。
11.根据权利要求9所述的集成电路结构,进一步包括:
多个凹槽,并且其中,基本上所述晶片中的每个所述切割槽均包括多个所述凹槽中的一个;所述凹槽具有倾斜侧壁或所述凹槽具有基本垂直的侧壁;
所述晶片中的每个所述切割槽均具有基本从每个所述切割槽的一端延伸至对端的凹槽。
12.一种集成电路结构,包括:
半导体芯片;
半导体衬底,在所述半导体芯片中,其中,所述半导体衬底具有边缘;
互连结构,在所述半导体衬底之上;
凹槽,在所述半导体芯片的边缘上并且从所述边缘的一端延伸至对端,其中,所述半导体衬底的边缘是所述半导体芯片的边缘的下部,并且其中,所述凹槽的底部比所述半导体衬底的顶面低;以及
第一绝缘膜,在所述互连结构之上并且延伸至所述凹槽中,其中,所述凹槽中的所述第一绝缘膜的第一边缘基本上平行于所述半导体衬底的所述边缘并且与所述半导体衬底的所述边缘水平分离;
第二绝缘膜,在所述晶片之上并且在所述第一绝缘膜之下,其中,所述第二绝缘膜包括在所述第一半导体芯片之上的第一部分,并且其中,所述第二绝缘膜的第一部分包括所述凹槽中的第一边缘;
其中,所述第一绝缘膜的第一部分的第一边缘向所述切割槽的中心延伸得比所述第二绝缘膜的第一部分的第一边缘远。
13.根据权利要求12所述的集成电路结构,其中,所述凹槽是围绕所述半导体芯片的凹口环的一部分;
所述的集成电路结构进一步包括在所述互连结构之上并且在所述第一绝缘膜之下的第二绝缘膜,其中,所述第二绝缘膜包括所述凹槽中的第二边缘;其中,所述第一边缘比所述第二边缘更接近所述半导体衬底的边缘;
所述凹槽具有基本上垂直的侧壁。
14.一种集成电路结构,包括:
半导体芯片;
半导体衬底,在所述半导体芯片中,其中,所述半导体衬底具有边缘;
互连结构,在所述半导体衬底之上;
凹槽,在所述半导体芯片的边缘上并且从所述边缘的一端延伸至对端,其中,所述半导体衬底的边缘是所述半导体芯片的边缘的一部分,并且其中,所述凹槽延伸至所述半导体衬底中;以及
第一绝缘膜,在所述半导体衬底之上并且延伸至所述凹槽中,其中,所述第一绝缘膜具有包括直接在所述凹槽之上的第一部分和所述凹槽外部的第二部分的顶面,并且其中,所述第一部分比所述第二部分低;
第二绝缘膜,在所述晶片之上并且在所述第一绝缘膜之下,其中,所述第二绝缘膜包括在所述第一半导体芯片之上的第一部分,并且其中,所述第二绝缘膜的第一部分包括所述凹槽中的第一边缘;
其中,所述第一绝缘膜的第一部分的第一边缘向所述切割槽的中心延伸得比所述第二绝缘膜的第一部分的第一边缘远。
15.根据权利要求14所述的集成电路结构,其中,所述凹槽中的第一绝缘膜的第一边缘基本平行于所述半导体衬底的边缘,并且与所述半导体衬底的所述边缘水平分离;
所述集成电路结构进一步包括:所述第二绝缘膜的顶面包括所述凹槽中的第二边缘,并且其中,所述第二边缘基本平行于所述半导体衬底的边缘并且与所述半导体衬底的边缘水平分离;
其中,所述第一边缘比所述第二边缘更接近所述半导体衬底的边缘。
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US8580657B2 (en) | 2013-11-12 |
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