KR101001530B1 - 웨이퍼 스크라이브 영역 내의 금속 감소 - Google Patents

웨이퍼 스크라이브 영역 내의 금속 감소 Download PDF

Info

Publication number
KR101001530B1
KR101001530B1 KR1020057013873A KR20057013873A KR101001530B1 KR 101001530 B1 KR101001530 B1 KR 101001530B1 KR 1020057013873 A KR1020057013873 A KR 1020057013873A KR 20057013873 A KR20057013873 A KR 20057013873A KR 101001530 B1 KR101001530 B1 KR 101001530B1
Authority
KR
South Korea
Prior art keywords
delete delete
wafer
metal
scribe
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020057013873A
Other languages
English (en)
Korean (ko)
Other versions
KR20050095630A (ko
Inventor
스캇 케이. 포즈덜
트렌트 에스. 윌링
라크시미 엔. 라마나싼
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20050095630A publication Critical patent/KR20050095630A/ko
Application granted granted Critical
Publication of KR101001530B1 publication Critical patent/KR101001530B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
KR1020057013873A 2003-01-27 2004-01-23 웨이퍼 스크라이브 영역 내의 금속 감소 Expired - Fee Related KR101001530B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/351,798 2003-01-27
US10/351,798 US6951801B2 (en) 2003-01-27 2003-01-27 Metal reduction in wafer scribe area

Publications (2)

Publication Number Publication Date
KR20050095630A KR20050095630A (ko) 2005-09-29
KR101001530B1 true KR101001530B1 (ko) 2010-12-16

Family

ID=32735850

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057013873A Expired - Fee Related KR101001530B1 (ko) 2003-01-27 2004-01-23 웨이퍼 스크라이브 영역 내의 금속 감소

Country Status (6)

Country Link
US (1) US6951801B2 (enExample)
JP (1) JP2006516824A (enExample)
KR (1) KR101001530B1 (enExample)
CN (1) CN1777978B (enExample)
TW (1) TWI325155B (enExample)
WO (1) WO2004073014A2 (enExample)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232448A1 (en) * 2003-05-23 2004-11-25 Taiwan Semiconductor Manufacturing Co. Layout style in the interface between input/output (I/O) cell and bond pad
CN100370580C (zh) * 2004-03-29 2008-02-20 雅马哈株式会社 半导体晶片及其制造方法
US7553700B2 (en) * 2004-05-11 2009-06-30 Gem Services, Inc. Chemical-enhanced package singulation process
US7223673B2 (en) * 2004-07-15 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device with crack prevention ring
JP4288229B2 (ja) * 2004-12-24 2009-07-01 パナソニック株式会社 半導体チップの製造方法
JP4471852B2 (ja) * 2005-01-21 2010-06-02 パナソニック株式会社 半導体ウェハ及びそれを用いた製造方法ならびに半導体装置
US7572738B2 (en) * 2005-05-23 2009-08-11 Sony Corporation Crack stop trenches in multi-layered low-k semiconductor devices
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
KR100672728B1 (ko) * 2005-07-12 2007-01-22 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7250670B2 (en) * 2005-09-27 2007-07-31 United Microelectronics Corp. Semiconductor structure and fabricating method thereof
CN100481455C (zh) * 2005-12-22 2009-04-22 中芯国际集成电路制造(上海)有限公司 具有不全接触通孔栈的密封环结构
US7511379B1 (en) * 2006-03-23 2009-03-31 National Semiconductor Corporation Surface mountable direct chip attach device and method including integral integrated circuit
US7732897B2 (en) * 2006-06-15 2010-06-08 Taiwan Semiconductor Manufacturing Co., Ltd Methods of die sawing and structures formed thereby
US7679195B2 (en) * 2006-06-20 2010-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. PAD structure and method of testing
JP2008066716A (ja) * 2006-08-10 2008-03-21 Matsushita Electric Ind Co Ltd 半導体装置
US7622364B2 (en) * 2006-08-18 2009-11-24 International Business Machines Corporation Bond pad for wafer and package for CMOS imager
US7566915B2 (en) * 2006-12-29 2009-07-28 Intel Corporation Guard ring extension to prevent reliability failures
US9601443B2 (en) * 2007-02-13 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Test structure for seal ring quality monitor
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US7674689B2 (en) * 2007-09-20 2010-03-09 Infineon Technologies Ag Method of making an integrated circuit including singulating a semiconductor wafer
KR20090046993A (ko) * 2007-11-07 2009-05-12 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
JP5583320B2 (ja) * 2007-12-05 2014-09-03 ピーエスフォー ルクスコ エスエイアールエル 半導体ウエハ及びその製造方法
US8013425B2 (en) * 2008-05-13 2011-09-06 United Microelectronics Corp. Scribe line structure for wafer dicing and method of making the same
US7821104B2 (en) * 2008-08-29 2010-10-26 Freescale Semiconductor, Inc. Package device having crack arrest feature and method of forming
US8022509B2 (en) * 2008-11-28 2011-09-20 United Microelectronics Corp. Crack stopping structure and method for fabricating the same
WO2010086952A1 (ja) * 2009-01-30 2010-08-05 パナソニック株式会社 半導体装置及びその製造方法
US8237246B2 (en) * 2009-02-12 2012-08-07 International Business Machines Corporation Deep trench crackstops under contacts
US8748295B2 (en) 2009-06-15 2014-06-10 Infineon Technologies Ag Pads with different width in a scribe line region and method for manufacturing these pads
JP5175803B2 (ja) * 2009-07-01 2013-04-03 新光電気工業株式会社 半導体装置の製造方法
US8357996B2 (en) * 2009-11-17 2013-01-22 Cree, Inc. Devices with crack stops
JP4649531B1 (ja) * 2009-12-08 2011-03-09 新光電気工業株式会社 電子装置の切断方法
JP2011134824A (ja) * 2009-12-24 2011-07-07 Elpida Memory Inc 半導体ウエハ、半導体ウエハの製造方法、および半導体装置
JP2011199123A (ja) * 2010-03-23 2011-10-06 Elpida Memory Inc 半導体装置およびその製造方法
US8531008B2 (en) * 2010-11-23 2013-09-10 Infineon Technologies Ag Material structure in scribe line and method of separating chips
US9331019B2 (en) 2012-11-29 2016-05-03 Infineon Technologies Ag Device comprising a ductile layer and method of making the same
US8659173B1 (en) * 2013-01-04 2014-02-25 International Business Machines Corporation Isolated wire structures with reduced stress, methods of manufacturing and design structures
US8937009B2 (en) 2013-04-25 2015-01-20 International Business Machines Corporation Far back end of the line metallization method and structures
US9490173B2 (en) * 2013-10-30 2016-11-08 Infineon Technologies Ag Method for processing wafer
CN104701271A (zh) * 2013-12-05 2015-06-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10553508B2 (en) 2014-01-13 2020-02-04 Nxp Usa, Inc. Semiconductor manufacturing using disposable test circuitry within scribe lanes
CN105025480B (zh) * 2014-04-29 2019-04-05 中国电信股份有限公司 用户卡数字签名验证的方法与系统
US9601354B2 (en) 2014-08-27 2017-03-21 Nxp Usa, Inc. Semiconductor manufacturing for forming bond pads and seal rings
JP6571344B2 (ja) * 2015-02-19 2019-09-04 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置
DE102017123846B4 (de) * 2017-10-13 2020-03-12 Infineon Technologies Austria Ag Leistungshalbleiter-Die und Halbleiterwafer umfassend einen Oxid-Peeling Stopper und Verfahren zum Verarbeiten eines Halbleiterwafers
US10734304B2 (en) 2018-11-16 2020-08-04 Texas Instruments Incorporated Plating for thermal management
CN111785686B (zh) * 2019-04-03 2023-08-15 华邦电子股份有限公司 切割晶圆的方法及晶粒
JP6817372B2 (ja) * 2019-06-13 2021-01-20 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． ウェーハダイシング方法およびダイ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030197289A1 (en) 2002-04-19 2003-10-23 Kulicke & Soffa Investments, Inc. Design of interconnection pads with separated probing and wire bonding regions
US20040219776A1 (en) 2002-12-30 2004-11-04 Cheolsoo Park Method for forming metal lines in a semiconductor device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246647A (ja) * 1984-05-22 1985-12-06 Nec Corp 半導体装置
US5136354A (en) * 1989-04-13 1992-08-04 Seiko Epson Corporation Semiconductor device wafer with interlayer insulating film covering the scribe lines
JPH05326697A (ja) * 1992-05-23 1993-12-10 Sony Corp 半導体装置の製造方法
JP2776457B2 (ja) * 1992-12-29 1998-07-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスのクラックストップ形成方法及び半導体デバイス
US5596226A (en) * 1994-09-06 1997-01-21 International Business Machines Corporation Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module
JPH08162456A (ja) * 1994-12-07 1996-06-21 Kawasaki Steel Corp バンプの製造方法
JP3493531B2 (ja) * 1995-02-03 2004-02-03 カシオ計算機株式会社 半導体装置の製造方法
JPH09306913A (ja) * 1996-05-15 1997-11-28 Citizen Watch Co Ltd 半導体装置およびその製造方法
JPH10154670A (ja) * 1996-11-26 1998-06-09 Toshiba Corp 半導体装置の製造方法
US5789302A (en) * 1997-03-24 1998-08-04 Siemens Aktiengesellschaft Crack stops
US6075280A (en) * 1997-12-31 2000-06-13 Winbond Electronics Corporation Precision breaking of semiconductor wafer into chips by applying an etch process
JPH11204525A (ja) * 1998-01-14 1999-07-30 Seiko Epson Corp 半導体装置の製造方法
JP2000252236A (ja) * 1999-03-03 2000-09-14 Toshiba Corp 半導体装置及びその製造方法
CN1138305C (zh) * 1999-05-27 2004-02-11 国际商业机器公司 含有导电熔丝的半导体结构及其制造方法
US6362524B1 (en) 2000-07-26 2002-03-26 Advanced Micro Devices, Inc. Edge seal ring for copper damascene process and method for fabrication thereof
JP2002217196A (ja) * 2001-01-17 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6881610B2 (en) * 2003-01-02 2005-04-19 Intel Corporation Method and apparatus for preparing a plurality of dice in wafers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030197289A1 (en) 2002-04-19 2003-10-23 Kulicke & Soffa Investments, Inc. Design of interconnection pads with separated probing and wire bonding regions
US20040219776A1 (en) 2002-12-30 2004-11-04 Cheolsoo Park Method for forming metal lines in a semiconductor device

Also Published As

Publication number Publication date
CN1777978A (zh) 2006-05-24
WO2004073014A2 (en) 2004-08-26
JP2006516824A (ja) 2006-07-06
CN1777978B (zh) 2010-07-21
US20040147097A1 (en) 2004-07-29
TW200416857A (en) 2004-09-01
US6951801B2 (en) 2005-10-04
WO2004073014A3 (en) 2005-04-21
KR20050095630A (ko) 2005-09-29
TWI325155B (en) 2010-05-21

Similar Documents

Publication Publication Date Title
KR101001530B1 (ko) 웨이퍼 스크라이브 영역 내의 금속 감소
KR100725565B1 (ko) 반도체 장치의 제조 방법
US7838424B2 (en) Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
JP4580867B2 (ja) 半導体装置の製造方法、半導体ウエハおよび半導体装置
JP4307284B2 (ja) 半導体装置の製造方法
CN101685794B (zh) 使用绝缘膜保护半导体芯片的侧壁
KR100682434B1 (ko) 반도체 장치 및 그 제조 방법
KR100679573B1 (ko) 반도체 장치의 제조 방법
US9230885B2 (en) Semiconductor structure and method for making same
KR20120004906A (ko) Ｕｂｍ 에칭 방법
US20080099913A1 (en) Metallization layer stack without a terminal aluminum metal layer
US20080070379A1 (en) Method of fabricating semiconductor device
KR20090075883A (ko) 알루미늄 단자 금속층이 없는 금속화층 스택
US7696615B2 (en) Semiconductor device having pillar-shaped terminal
KR100891522B1 (ko) 웨이퍼 레벨 패키지의 제조방법
US12237219B2 (en) Contact with bronze material to mitigate undercut
US20090026585A1 (en) Semiconductor Device and Method for Manufacturing the same
US20210118738A1 (en) Semiconductor packages and methods of packaging semiconductor devices
JP4845986B2 (ja) 半導体装置
US12438086B2 (en) Semiconductor package and method of forming the same with dielectric layer disposed between protective mold structure and stepped structure of side portion of semiconductor die
CN117219601A (zh) 一种重新布线层、封装结构以及相应的制备方法
KR20050059617A (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20131125

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20141124

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20151124

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20181210

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20181210