JP2006501652A - 耐クラック性の相互接続モジュール - Google Patents

耐クラック性の相互接続モジュール Download PDF

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Publication number
JP2006501652A
JP2006501652A JP2004540216A JP2004540216A JP2006501652A JP 2006501652 A JP2006501652 A JP 2006501652A JP 2004540216 A JP2004540216 A JP 2004540216A JP 2004540216 A JP2004540216 A JP 2004540216A JP 2006501652 A JP2006501652 A JP 2006501652A
Authority
JP
Japan
Prior art keywords
chip
die
substrate
dielectric
mounting surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004540216A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006501652A5 (https=
Inventor
ロビン・イー・ゴーレル
マーク・エフ・シルベスター
ドナルド・アール・バンクス
マイケル・ディ・ホルクーム
ウィリアム・ブイ・バラード
孝一 広沢
定信 佐藤
輝彦 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
3M Innovative Properties Co
Original Assignee
NEC Electronics Corp
3M Innovative Properties Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp, 3M Innovative Properties Co filed Critical NEC Electronics Corp
Publication of JP2006501652A publication Critical patent/JP2006501652A/ja
Publication of JP2006501652A5 publication Critical patent/JP2006501652A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2004540216A 2002-09-27 2003-09-24 耐クラック性の相互接続モジュール Pending JP2006501652A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US41446102P 2002-09-27 2002-09-27
US10/668,881 US20040104463A1 (en) 2002-09-27 2003-09-23 Crack resistant interconnect module
PCT/US2003/030060 WO2004030096A2 (en) 2002-09-27 2003-09-24 Crack resistant interconnect module

Publications (2)

Publication Number Publication Date
JP2006501652A true JP2006501652A (ja) 2006-01-12
JP2006501652A5 JP2006501652A5 (https=) 2006-11-02

Family

ID=32045287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004540216A Pending JP2006501652A (ja) 2002-09-27 2003-09-24 耐クラック性の相互接続モジュール

Country Status (8)

Country Link
US (1) US20040104463A1 (https=)
EP (1) EP1543559A2 (https=)
JP (1) JP2006501652A (https=)
KR (1) KR20050075340A (https=)
CN (1) CN1685505A (https=)
AU (1) AU2003275208A1 (https=)
TW (1) TW200421563A (https=)
WO (1) WO2004030096A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9566361B2 (en) 2010-03-31 2017-02-14 Incorporated Administrative Agency, National Agriculture And Food Research Organization Method for catalyzing a fenton reaction
JP2022127112A (ja) * 2021-02-19 2022-08-31 テルモ株式会社 ステントの製造方法およびステント

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003298196A (ja) * 2002-04-03 2003-10-17 Japan Gore Tex Inc プリント配線板用誘電体フィルム、多層プリント基板および半導体装置
CN100401486C (zh) * 2002-08-09 2008-07-09 富士通株式会社 半导体装置及其制造方法
JP2006120935A (ja) * 2004-10-22 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
FI20051228L (sv) * 2005-12-01 2007-07-27 Zipic Oy Komponentlåda med mikrokrets
US20090223700A1 (en) * 2008-03-05 2009-09-10 Honeywell International Inc. Thin flexible circuits
KR101184375B1 (ko) * 2010-05-10 2012-09-20 매그나칩 반도체 유한회사 패드 영역의 크랙 발생을 방지하는 반도체 장치 및 그 제조 방법
US20130027894A1 (en) * 2011-07-27 2013-01-31 Harris Corporation Stiffness enhancement of electronic substrates using circuit components

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4496793A (en) * 1980-06-25 1985-01-29 General Electric Company Multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion
US4890194A (en) * 1985-11-22 1989-12-26 Texas Instruments Incorporated A chip carrier and mounting structure connected to the chip carrier
US6210862B1 (en) * 1989-03-03 2001-04-03 International Business Machines Corporation Composition for photoimaging
JP2656416B2 (ja) * 1991-12-16 1997-09-24 三菱電機株式会社 半導体装置および半導体装置の製造方法、並びに半導体装置に用いられる複合基板および複合基板の製造方法
US5354955A (en) * 1992-12-02 1994-10-11 International Business Machines Corporation Direct jump engineering change system
JP3112059B2 (ja) * 1995-07-05 2000-11-27 株式会社日立製作所 薄膜多層配線基板及びその製法
EP0797084B1 (de) * 1996-03-23 2001-01-17 Endress + Hauser GmbH + Co. Verfahren zum Herstellen von kapazitiven, in Nullpunkt-Langzeit-Fehlerklassen sortierten Keramik-Absolutdruck-Sensoren
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
AU5238898A (en) * 1996-11-08 1998-05-29 W.L. Gore & Associates, Inc. Method for reducing via inductance in an electronic assembly and device
US5838063A (en) * 1996-11-08 1998-11-17 W. L. Gore & Associates Method of increasing package reliability using package lids with plane CTE gradients
WO1998020528A1 (en) * 1996-11-08 1998-05-14 W.L. Gore & Associates, Inc. METHOD FOR IMPROVING RELIABILITY OF THIN CIRCUIT SUBSTRATES BY INCREASING THE Tg OF THE SUBSTRATE
US5888631A (en) * 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Method for minimizing warp in the production of electronic assemblies
US5879786A (en) * 1996-11-08 1999-03-09 W. L. Gore & Associates, Inc. Constraining ring for use in electronic packaging
JP2001525120A (ja) * 1996-11-08 2001-12-04 ダブリュ．エル．ゴア アンド アソシエイツ，インコーポレイティド ブラインドおよびスルーの両マイクロ―ヴァイアの入口の品質を向上するために吸光コーティングを用いる方法
US5868950A (en) * 1996-11-08 1999-02-09 W. L. Gore & Associates, Inc. Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques
US6103992A (en) * 1996-11-08 2000-08-15 W. L. Gore & Associates, Inc. Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias
US5731047A (en) * 1996-11-08 1998-03-24 W.L. Gore & Associates, Inc. Multiple frequency processing to improve electrical resistivity of blind micro-vias
US5888630A (en) * 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly
US5900312A (en) * 1996-11-08 1999-05-04 W. L. Gore & Associates, Inc. Integrated circuit chip package assembly
JP2982729B2 (ja) * 1997-01-16 1999-11-29 日本電気株式会社 半導体装置
US5900675A (en) * 1997-04-21 1999-05-04 International Business Machines Corporation Organic controlled collapse chip connector (C4) ball grid array (BGA) chip carrier with dual thermal expansion rates
US5973337A (en) * 1997-08-25 1999-10-26 Motorola, Inc. Ball grid device with optically transmissive coating
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
US6075710A (en) * 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips
JP4311774B2 (ja) * 1998-03-11 2009-08-12 富士通株式会社 電子部品パッケージおよびプリント配線板
US6046910A (en) * 1998-03-18 2000-04-04 Motorola, Inc. Microelectronic assembly having slidable contacts and method for manufacturing the assembly
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6291899B1 (en) * 1999-02-16 2001-09-18 Micron Technology, Inc. Method and apparatus for reducing BGA warpage caused by encapsulation
US6337228B1 (en) * 1999-05-12 2002-01-08 Amkor Technology, Inc. Low-cost printed circuit board with integral heat sink for semiconductor package
TW512653B (en) * 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
US6497943B1 (en) * 2000-02-14 2002-12-24 International Business Machines Corporation Surface metal balancing to reduce chip carrier flexing
US6570245B1 (en) * 2000-03-09 2003-05-27 Intel Corporation Stress shield for microelectronic dice
JP3446826B2 (ja) * 2000-04-06 2003-09-16 沖電気工業株式会社 半導体装置及びその製造方法
JP3450279B2 (ja) * 2000-07-27 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2002093853A (ja) * 2000-09-07 2002-03-29 Internatl Business Mach Corp <Ibm> プリント配線板およびフリップチップ実装方法
US6448639B1 (en) * 2000-09-18 2002-09-10 Advanced Semiconductor Engineering, Inc. Substrate having specific pad distribution
US6600224B1 (en) * 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6570259B2 (en) * 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US6847527B2 (en) * 2001-08-24 2005-01-25 3M Innovative Properties Company Interconnect module with reduced power distribution impedance
SG104279A1 (en) * 2001-11-02 2004-06-21 Inst Of Microelectronics Enhanced chip scale package for flip chips

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9566361B2 (en) 2010-03-31 2017-02-14 Incorporated Administrative Agency, National Agriculture And Food Research Organization Method for catalyzing a fenton reaction
US9566360B2 (en) 2010-03-31 2017-02-14 Incorporated Administrative Agency National Agriculture And Food Research Organization Fenton reaction catalyst using coffee grounds or tea dregs as raw material
JP2022127112A (ja) * 2021-02-19 2022-08-31 テルモ株式会社 ステントの製造方法およびステント
JP7506619B2 (ja) 2021-02-19 2024-06-26 テルモ株式会社 ステントの製造方法およびステント
JP2024107436A (ja) * 2021-02-19 2024-08-08 テルモ株式会社 ステントの製造方法およびステント

Also Published As

Publication number Publication date
AU2003275208A8 (en) 2004-04-19
WO2004030096A2 (en) 2004-04-08
EP1543559A2 (en) 2005-06-22
TW200421563A (en) 2004-10-16
KR20050075340A (ko) 2005-07-20
CN1685505A (zh) 2005-10-19
US20040104463A1 (en) 2004-06-03
AU2003275208A1 (en) 2004-04-19
WO2004030096A3 (en) 2004-06-17

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