JP2006501652A - Crack resistant interconnect module - Google Patents

Abstract

A substrate having a chip mounting surface and a board mounting surface defining contact pads for mounting corresponding pads on the chip and the board, wherein the substrate board surface covers at least one chip mounting surface area near the chip corner; A stacked flip chip interconnect package containing one solid surface. In one embodiment, the solid surface comprises a dielectric material and is optionally covered with a solder mask or coverlay material. In an alternative embodiment, the solid surface comprises metal and is optionally covered with a solder mask or coverlay material.

Description

  The present invention relates to interconnect modules for use in integrated circuit chips.

  Multilayer interconnect modules are widely used in the semiconductor industry to mechanically support integrated circuit chips and to electrically attach the chips to printed wiring boards. An interconnect module can be configured to support a single chip or multiple chips and is commonly referred to as SCM (single chip module) or MCM (multichip module).

  The interconnect module provides an interconnect that serves to electrically couple the integrated circuit chip to signal lines, power lines and other components on the printed wiring board. In particular, the interconnect module provides an interconnect that redistributes the high density input / output (I / O) of the chip to the corresponding I / O of the printed wiring board. In addition to electrical interconnection, the interconnection module also serves to mechanically couple the chip to the printed wiring board and performs other functions such as heat dissipation and environmental protection.

  An integrated circuit (IC) with a low coefficient of thermal expansion (CTE) (about 2.6 ppm / ° C. for silicon) is relatively thin (<0.75 mm) with a relatively high CTE (> 15 ppm / ° C.) and is therefore flexible. After bonding to the package substrate at a high temperature, inherent tensile stresses and strains are generated in the package as the substrate is cooled to a low temperature. Some of these arise directly from the bonding of the two components. In such a package, the stress or strain in a particular area increases to a level that causes cracks in the dielectric and / or conductor material of the substrate. This can occur after a single low temperature exposure due to breakage or after repeated exposure due to fatigue.

To improve this situation, according to the present invention, the interconnect module incorporates a plurality of alternating dielectric and metal layers stacked to form a single structure. The stacked interconnect structure incorporates a number of vias and patterned signal layers that provide conductive interconnect paths between the chip, printed wiring board, and various layers within the interconnect module. The interconnect module includes a chip mounting surface and a board mounting surface that define contact pads for mounting corresponding pads to the chip and board, respectively, via solder balls. Various layers are selected that exhibit a coefficient of thermal expansion (CTE) that promotes reliable interconnection with the chip and PWB.
US Pat. No. 6,021,564 US Pat. No. 5,888,630 US Pat. No. 6,018,196 US Pat. No. 5,983,974 US Pat. No. 5,836,063 US Pat. No. 5,731,047 US Pat. No. 5,841,075 US Pat. No. 5,868,950 US Pat. No. 5,888,631 US Pat. No. 5,900,312 US Pat. No. 6,011,697 US Pat. No. 6,103,992 US Pat. No. 6,127,250 US Pat. No. 6,143,401 US Pat. No. 6,183,592 US Pat. No. 6,203,891 US Pat. No. 6,248,959

  The present invention provides a flip chip integrated circuit (IC) package that has a reduced tendency to crack or is not prone to cracking. The flip chip package of the present invention includes a ball grid for a package that includes at least one solid plane and a region around at least one corner of an integrated circuit (IC, also referred to as “die”) or “die shadow”. It is on the array (BGA) side. The size and shape of the area covered by the surface will vary based on other design features of the package. These surfaces may be used as power or ground connections by using a solder mask to define the BGA pads on the surface. An important aspect of the present invention is to provide areas without geometric discontinuities on the BGA sides in the area near the die corner.

  In at least one embodiment of the present invention, a stacked flip chip interconnect package includes a substrate having a chip mounting surface and a board mounting surface defining contact pads for mounting corresponding pads on the chip and the board, The board surface includes at least one solid surface that covers a chip mounting surface area near the chip corner. The solid surface includes a dielectric material and is optionally covered with a solder mask or coverlay material.

  In at least one embodiment of the present invention, the flip chip package includes at least one solid surface, and the region near the chip corner is comprised of a solid metal surface optionally covered with a solder mask or coverlay material. Yes.

  In another embodiment of the present invention, the solid surface includes a metal solid surface covered with a solder mask material having openings defining BGA pads.

  While other features of the flip chip IC package of the present invention vary, it is desirable that the package remain relatively thin and flexible.

The following terms have the following meanings as used herein.
1. As used herein, the term “conductive” means conducting electricity.
2. The term “geometric discontinuity” means a feature such as a contact pad or opening that interrupts a continuous region of material.
3. As used herein, the term “interconnect substrate” corresponds to the terms “package substrate”, “flexible package substrate”, “rigid package substrate”, and the like.
4). The term “solid surface” means a region of a single material without geometric discontinuities.

  Interconnect module 100 may incorporate a series of alternating dielectric and metal layers that are stacked to form a single interconnect substrate 110 (shown as a single material), as shown in FIG. The laminated interconnect substrate 110 includes a number of vias and patterned signal layers (not shown) that provide conductive interconnect paths between the chip 120, the printed wiring board 130, and various layers in the interconnect module. May be incorporated. 3 and 4 are detailed schematic views of the laminated interconnect substrate. The interconnect module includes a chip mounting surface 125 and a board mounting surface 135 that define contact pads for mounting corresponding pads to the chip and board via solder balls 128, 138, respectively. And electrical and mechanical connections between the interconnect substrate and the interconnect substrate and printed wiring board (PWB). The various layers are selected to have a coefficient of thermal expansion (CTE) that facilitates reliable interconnection with the chip and PWB. The interconnect module also includes a stiffening member 140 that is bonded to the interconnect substrate 110 of the chip mounting surface 125 by an adhesive 145, with the chip located in the center of the stiffening member. An underfill adhesive 170 may be disposed between the chip mounting surface 125 of the interconnect substrate 110 and the lower side of the chip, thereby encapsulating the chip mounting solder balls 128. Finally, the lid assembly 150 may be bonded to the upper side of the stiffening member with an additional adhesive layer 155. A thermally conductive adhesive or elastomer 160 material may be interposed between the top surface of the chip 120 and the lid assembly 150 to assist in dissipating the heat generated by the chip during operation.

  An IC chip 120 with a low coefficient of thermal expansion (CTE) (about 2.6 ppm / ° C. for silicon) is relatively thin (<0.75 mm) with a relatively high CTE (> 15 ppm / ° C.), thus a flexible package substrate After bonding with 110 at high temperatures, large inherent tensile stresses and strains are generated in the package as the substrate is cooled to low temperatures. Some of these arise directly from the bonding of the two components, but the flexibility of the package substrate in response to direct intrinsic stress or strain may be suppressed or partially suppressed. Such suppression can occur when the stiffening member 140 is used in a package such as a ring or lid assembly 150.

  In such a package substrate, the stress or strain in a specific region increases to a level that causes cracks in the dielectric and / or conductor material constituting the substrate. This can occur after a single low temperature exposure due to breakage or after repeated exposure due to a fatigue process.

  It has been found that cracks are formed in two regions of the interconnect module part with a thermal cycle between + 125 ° C. and −40 ° C. or −55 ° C. 2a and 2b show the location of where the crack is formed in the BGA interconnect module 200. FIG. FIG. 2b is an enlarged view of the gray circular region of FIG. 2a. The figure shows an array of solder ball pads 240 on the BGA side of the substrate for an interconnect module. The first region is just outside the die corner 210 and the end of the die 220 is shown as a dark line, and in extreme cases continues down along the end of the die. The presence of cracks 230 is shown in solder ball pads 240 near the corners of the die.

  Experiments have demonstrated that it was formed by a typical fatigue process. Cracks occur from the edge of the metal feature, most commonly the BGA surface of the interconnect module (350 in FIG. 3, metal layer 440 in FIG. 4) near the metal layer (302 in FIG. 3, 402 in FIG. 4). Of BGA pads (390 in FIG. 3, 490 in FIG. 4). Cracks spread to adjacent metal and dielectric layers (345, 365 and 366 in FIG. 3, 435, 463 and 464 in FIG. 4). For example, a growing dielectric crack will contact the signal trace in the metal layer before the planar layer and the trace will crack and not be electrically connected. Cracks often progress until they reach a solid surface, such as the metal power surface (340) of FIG. 3 or the metal “core” surface (430) of FIG. These surfaces act as “crack stoppers” because they do not have geometric discontinuities that easily spread cracks. When a dielectric material is used, a crack stop surface can be formed. However, since copper originally has high toughness compared to some dielectric materials, a metal such as copper is preferable.

  FIG. 3 is a schematic diagram of a portion of an interconnect substrate that can be used in conjunction with the present invention. FIG. 3 shows alternating metal layers (320 (pad and / or surface), 325 (signal), 330 (power or ground), 335 (core), 340 (power or ground), 345 (signal) and 350 (pad). And / or surface) and seven interconnect substrates 300 made by stacking dielectric layers (361, 362, 363, 364, 365 and 366), which are shown in FIG. Are arranged symmetrically around the core metal layer 335. That is, each dielectric or metal layer formed on one side of the core layer 335 has a corresponding layer of the same material formed on the opposite side of the core layer. Have.

  As further shown in FIG. 3, the first via 380 extends from the metal layer 320 through the dielectric layer 361 and ends with the metal layer 325. Second via 375 begins with metal layer 325, extends through dielectric layers 362, 363, 364, and 365 and ends with metal layer 345. Third via 370 extends from metal layer 345 through dielectric layer 366 and ends with metal layer 350. Each via 370, 375, 380 is plated with a conductive material using vapor deposition techniques well known in the microelectronic manufacturing industry. Alternatively, each via 370, 375, 380 is filled with a conductive material to define a conductive path. One skilled in the art can use a combination of vias, including blind vias, buried vias and through vias to provide electrical connection between bond pad 357 on die attach surface 304 and bond pad 390 on BGA attach surface 302. You will see that you can.

  Solder masks 310, 315 can be applied to the chip mounting surface 304 and the BGA mounting surface 302. The solder mask is typically made of a filled epoxy material. Each solder mask 310, 315 exposes a contact or bond pad proximate to each via 370, 375, 380. For example, solder mask 310 exposes contact pad 357 and solder mask 315 exposes contact pad 390. When the solder balls 355 in alignment with the chip are aligned with the contact pads 357, heated and reflowed, electrical and mechanical bonds can be formed with the contact pads. Similarly, a solder ball (not shown) associated with the bond can be aligned with the contact pad 390, heated, and reflowed to form an electrical and mechanical bond between the contact pad and the PWB.

  The dielectric layers 361, 362, 363, 364, 365, and 366 include a polyimide-polyimide laminate, an epoxy resin, a liquid crystal polymer, an organic material, or at least partly from polytetrafluoroethylene, with or without fillers. It may be formed from a stack of high temperature organic dielectric substrate materials, such as the dielectric material being constructed. In one embodiment, the dielectric layers 361, 362, 363, 364, 365 and 366 are made of organic material such as polytetrafluoroethylene (PTFE), in particular “ePTFE” impregnated with expanded PTFE or cyanate ester and epoxy. Has been created. The PTFE material may in particular be an expanded polytetrafluoroethylene matrix containing a mixed cyanate ester-epoxy adhesive and an inorganic filler.

  Metal layers 320, 325, 330, 335, 340, 345 and 350 may be formed from copper. Other suitable materials may be aluminum, gold, silver, or the like. In this example, metal layers 320, 325, 330, 340, 345 and 350 each have a thickness in the range of about 5-14 microns. In one embodiment, the thickness of each metal layer 320, 325, 330, 345 and 350 is about 12 microns. The thickness of the core metal layer 335 ranges from about 5 to 50 microns. The thicknesses of the dielectric layers 361, 362, 363, 364, 365 and 366 are each in the range of about 20 to 70 microns. In one embodiment, the thickness of each dielectric 361, 362, 363, 364, 365 and 366 layer is about 36 microns.

  Various layers of the interconnect substrate 300 can be stacked and stacked using heat and pressure. For example, all layers can be stacked into a stack at the same time. Alternatively, the layers can be built into the metal core layer 335 at a time or gradually with one or two additional layers added at each lamination step. During lamination, the dielectric layers 361, 362, 363, 364, 365 and 366 are melted and flowed to obtain a monolithic bulk dielectric material 360.

  The through via can be formed following the stacking of the interconnect substrate 300. In particular, vias can be formed by drilling or laser ablation processes, for example, as described in US Pat. No. 6,021,564. After lamination, solder masks 310 and 315 are added to the interconnect substrate 300. Solder masks 310 and 315 are patterned to define contact pads 357 and 390 that receive solder balls from chips 355 and PWB (not shown), respectively.

  FIG. 4 is a schematic diagram of a portion of an interconnect substrate that can be used in conjunction with the present invention. FIG. 4 shows a five-layer interconnect substrate manufactured by stacking alternating series of metal layers (420, 425, 430 (core), 435, 440) and dielectric layers (461, 462, 463, 464). 400 is shown. The metal and dielectric layers shown in FIG. 4 are arranged symmetrically around the core metal layer 430. That is, each dielectric or metal layer formed on one side of the core layer 430 has a corresponding layer of the same material formed on the opposite side of the core layer.

  As further shown in FIG. 4, the first via 480 extends from the metal layer 420 through the dielectric layer 461 and ends with the metal layer 425. The second via 475 begins with the metal layer 425, extends through the dielectric layers 462, 463, and ends with the metal layer 435. The third via 470 extends from the metal layer 435 through the dielectric layer 464 and ends with the metal layer 440. Each via 470, 475, 480 is plated with a conductive material using vapor deposition techniques well known in the microelectronic manufacturing industry. Alternatively, each via 470, 475, 480 is filled with a conductive material to define a conductive path. Those skilled in the art can use a combination of vias, including blind vias, buried vias and through vias to provide electrical connection between bond pad 457 on die attach surface 404 and bond pad 490 on BGA attach surface 402. You will see that you can.

  Solder masks 410, 415 can be applied to chip mounting surface 404 and BGA mounting surface 402. Each solder mask 410, 415 exposes a contact or bond pad proximate to each via 470, 480. For example, the solder mask 410 exposes the contact pads 457 and the solder mask 415 exposes the contact pads 490. When the solder balls 455 in alignment with the chip are aligned with the contact pads 457, heated and reflowed, electrical and mechanical bonds can be formed with the contact pads. Similarly, a solder ball (not shown) associated with the bond can be aligned with the contact pad 490, heated, and reflowed to form an electrical and mechanical bond between the contact pad and the PWB.

  The dielectric layers 461, 462, 463, and 464 include a polyimide and a polyimide laminate, an epoxy resin, a liquid crystal polymer, an organic material, or a dielectric composed at least in part of polytetrafluoroethylene, with or without a filler. It may be formed from a stack of high temperature organic dielectric substrate materials such as materials. In one embodiment, the dielectric layers 461, 462, 463, 464 are made of an organic material such as polytetrafluoroethylene (PTFE), particularly expanded PTFE or “ePTFE” impregnated with cyanate ester and epoxy. . The PTFE material may in particular be an expanded polytetrafluoroethylene matrix containing a mixed cyanate ester-epoxy adhesive and an inorganic filler.

  The metal layers 420, 425, 430, 435, and 440 may be made of copper. Other suitable materials may be aluminum, gold, silver, or the like. In this embodiment, the metal layers 420, 425, 430, 440 each have a thickness in the range of about 5-14 microns. In one example, the thickness of each metal layer 420, 425, 435 and 440 is about 12 microns. The thickness of the core metal layer 430 ranges from about 5 to 50 microns. The thicknesses of the dielectric layers 461, 462, 463, 464 are each in the range of about 20-70 microns. In one embodiment, the thickness of each dielectric 461, 462, 463, 464 layer is about 36 microns.

  Various layers of the interconnect substrate 400 can be stacked using heat and pressure. For example, all layers can be stacked into a stack at the same time. Alternatively, the layers can be built into the metal core layer 430 at one time or gradually with one or two additional layers added at each lamination step. During lamination, the dielectric layers 461, 462, 463, 464 are melted and flowed to obtain a monolithic bulk dielectric material 460.

  The through via can be formed following the stacking of the interconnect substrate 400. In particular, vias can be formed by drilling or laser ablation processes, for example, as described in US Pat. No. 6,021,564. After lamination, solder masks 410 and 415 are added to the interconnect substrate 400. Solder masks 410 and 415 are patterned to define contact pads 457 and 490 that receive solder balls from chips 455 and PWB (not shown), respectively.

  The interconnect substrate 300 or 400 can accept a “flip chip” integrated circuit. In flip chip mounting, a solder ball is placed on a die (eg, a chip), the chip is turned over, the chip is aligned with a contact pad on a substrate such as interconnect substrate 300 or 400, and the solder ball is reflowed in a furnace. Create a bond between the chip and the substrate. In this manner, the contact pads are not limited to the periphery as in wire bonding or tape automated bonding (TAB) technology, but are distributed over the entire chip surface. As a result, the maximum number of I / O and available power / ground terminals is increased and signal and power / ground interconnections are made more efficient by the chip.

  One skilled in the art will appreciate that the types of interconnect substrates that reflect the above embodiments may contain additional layers including embedded capacitor layers, metal layers, dielectric layers, and the like. . Depending on the requirements of the final interconnect module, it is also possible to produce interconnect substrates with fewer dielectric and metal layers.

  Die corner cracks are primarily formed from mechanical constraints imposed by rigid rings and / or lids. As shown in FIG. 5a, the assembled module 500a is often in an unstressed state at high temperatures that are close to being used to gel and cure various adhesive materials during the assembly process. However, as shown in FIG. 5b, when cooled to a low temperature, if the CTE mismatch between the die 510b and the other components of the assembly module 500b, particularly between the die and the interconnect substrate 520b, the package is recessed downwards. It becomes a shape. However, the rigid ring 530 prevents this and instead keeps the area of the covering substrate in a flat shape. At the transition between the concave cross section down the area under the die and the wide flat cross section of the rigid ring, a gap is created between the die and the rigid ring as shown schematically in FIG. 5b. This change in the shape of the short distance creates a tensile bending strain on the BGA side 540 of the substrate. This is especially true in the region near the die corner 550 because there is the same curvature in both the x and y directions.

  The sharper the change in shape, the more strain is present at the die corner and in the gap 560 between the die 510 and the stiffener ring 530. Conversely, as the shape changes gradually, the distortion decreases. Thus, one approach that can be taken to alleviate the problem is to increase the spacing between the die and the reinforcement ring. The wider the distance between the die and the reinforcement ring, the lower the critical strain. Smaller solid surface areas can be used when the critical strain is lower.

  For example, in W. Newark, Delaware. L. In the case of a substrate using an expanded polytetrafluoroethylene dielectric material available under the trade name MICROLAM from WL Gore and Associates, Newark, DE. In order to calculate the strain, the mechanical properties of the MICROLAM dielectric must be considered. First, the bending fracture strain of microram was measured and found to be 0.47% ± 0.15%. Second, the microtram fracture toughness was measured and is shown as a function of temperature in FIG. Finally, the fatigue properties of the material were measured. It is shown in FIG.

式中、Ｎ_ｆは不合格サイクルであり、Ｋ_Ｉは応力強さ因子であり、Ｋ_ＩＣは限界応力強度または破断靭性である。 Data show power law dependence on stress intensity.

Wherein, N _f is the failure cycle, K _I is the stress intensity factor, K _IC is the critical stress intensity or breaking toughness.

The storage cycle versus failure requirement required in the electronics industry is 10,000 cycles. From FIG. 7, the K _I / K _IC ratio is about 0.7. In order to achieve K _I １σ ₁ ∝ε ₁ (for isotropic homogeneous materials), the local strain must be kept below 0.7 or 0.33% of the breaking strain.

  FIG. 8 shows a detailed finite element model of 9 mm × 9 mm pieces of seven metal layer package substrates. FIG. 9 shows the stress in the BGA side dielectric around a single BGA pad when uniform biaxial strain is applied to the model of FIG. A region of high strain exists immediately around the edge of the BGA pad 1000 as indicated by the white ring 1010. FIG. 10 shows the degree of localization of this high stress region. The high stress or strain region is only about 75 μm wide and about 25 μm deep. The magnitude of high stress or strain in this region is approximately twice the nominal stress or strain.

  It has been found that cracks in MICROLAM dielectric material in the die corner region can be eliminated by maintaining a nominal strain of less than 0.17%, which can provide a possible solution to the die corner crack problem. . However, in the absence of strain concentrations caused by BGA pads or other geometric discontinuities, the nominal stress can be as high as 0.34% without forming cracks during thermal cycling.

  According to the present invention, a region that is not geometrically discontinuous on the BGA mounting surface in the region near the die corner is provided. This is done according to embodiments where the BGA mounting surface area near one or more die corners optionally comprises a solid surface of dielectric material covered with a solid layer of solder mask or coverlay material.

  In other embodiments, the region near the one or more die corners optionally comprises a solid surface of metal covered with a solid layer of solder mask or coverlay material.

  In yet another embodiment, the region near the one or more die corners consists of a solid metal surface covered with a solder mask having openings formed to define the BGA pads. This embodiment provides the advantages of a solid surface area near the die corner while making the area functional. Because most metals have higher strength and ductility than most dielectric materials, it is more desirable to use a metal surface than a dielectric surface. It is desirable to use a metal surface for the opening of the cover solder mask. This is primarily because some of the pad locations can be used to form mechanical interconnects (higher stiffness and support) in the PWB. Second, these pad locations bonded to the metal surface can be used to make electrical connections to power or ground, eliminating the complete loss of beneficial I / O connections. This helps to eliminate the increased package dimensions and the ultimate cost for both manufacturers and users.

  The dimensions of the solid surface are: die size and thickness, substrate thickness, dielectric material properties, reinforcement thickness and material, die-reinforcement gap, lid thickness and material, underfill properties (modulus, glass transition temperature , Gel temperature, etc.).

  An appropriate size of the solid surface can be obtained using a finite element model. FIG. 11 shows a 40 mm square package with a die-reinforcer spacing (3 mm (FIGS. 11a, 5 mm (FIG. 11b) and 7 mm (FIG. 11c)) with a 18.5 mm die and a 1.0 mm thick lid. The high strain region 1210 is in the vicinity of the die corner 1200 where the strain is greater than the critical strain at which cracking occurs, according to an aspect of the invention described herein, of the final interconnect module. During assembly, testing or use, if the geometric discontinuity causes cracks, the area of the solid surface can be adjusted and positioned. It is preferred that it is extended because the end of the solid surface itself is discontinuous and begins to crack when the critical strain is exceeded. , The critical strain levels, micro ram (MICROLAM) dielectric 95% confidence interval of the experimental fracture strain for materials 1/3, i.e. set to a value equal 0.11%.

  As can be seen from FIGS. 11a-11c, as the die-stiffener gap increases, the required surface area shrinks considerably. The aspects of the invention described herein allow the creation of general design rules, simplifying the design of these IC packages by reducing the need for a complete detailed finite element model for each design. The

式中、ｘおよびｙはミリメートル単位である。要素ａおよびｂは図１２に示すように測定値である。同じく図１２に示すように、この楕円の中心は、ダイコーナー１２１０を二分して、ダイ補強材リング１２５０の出発端部まで延在する線と一致する楕円の短軸と対角線に沿ってダイコーナーから外へ距離「ｄ」に位置している。ダイ補強材リング１２５０は金属または誘電体で作成してよい。いくつかのパラメータは、ソリッド面材料が金属か誘電体かによって異なる。高歪み領域はまた、ソリッド面を含む材料に応じて異なる。図１２に、１つのダイコーナー領域の楕円領域を示す。この楕円領域の外側にあるパッケージのＢＧＡの平均応力レベルは、通常の熱サイクル条件下でクラックが始まる、または広がるのに十分なレベルに達していない。 In at least one embodiment, the metal surface is disposed at one or more die corners of the BGA pad layer (eg, metal layer 350 of FIG. 3 or, eg, metal layer 440 of FIG. 4). Each metal surface contains an entire BGA pad in contact with an elliptical area of the size and shape defined by the following equation:

Where x and y are in millimeters. Elements a and b are measured values as shown in FIG. As also shown in FIG. 12, the center of this ellipse bisects the die corner 1210 and dies along the minor axis and diagonal of the ellipse that coincides with the line extending to the starting end of the die reinforcement ring 1250. It is located at a distance “d” from the outside. The die reinforcement ring 1250 may be made of metal or dielectric. Some parameters depend on whether the solid surface material is metal or dielectric. High strain regions also vary depending on the material containing the solid surface. FIG. 12 shows an elliptical area of one die corner area. The average stress level of the BGA of the package outside this elliptical area does not reach a level sufficient to initiate or spread cracks under normal thermal cycling conditions.

  The values of a, b and d vary with the spacing between the die and the reinforcement ring (S in FIG. 12) as shown in the table below.

  In practical application, if the die corner coincides with the BGA pad position, the solid surface must extend at a distance equal to at least two rows of BGA beyond the die end and one row under the die. I must.

  FIG. 13 a shows an embodiment of a solid surface covering the BGA pad layer region near the die corner 1310 formed at the intersection of the die end 1320. In this embodiment, the solid surface is formed by providing an unpatterned region 1330 (ie, no solder ball pad 1340) of the BGA pad layer at and around the die corner.

  FIG. 13b shows another embodiment similar to that shown in FIG. 13a. However, in FIG. 13b, the unpatterned region 1330 is physically separated from the rest of the BGA pad layer by channel 1335. The channel 1335 is formed by removing material from the BGA pad layer or masking the channel when the material-forming BGA pad layer is deposited.

  Solid surfaces are also formed by adding a layer of unpatterned material to one or more die corners and surrounding BGA pad layers (whether or not the BGA pad layers are patterned). . Additional layers may extend under the die or may be adjacent to the die corners and adjacent portions of the die ends. The layer is a metal or dielectric material.

  Two packages were built, packaged and assembled (package A) and not packaged (package B). They were identical except for the crack reduction feature. Both used a 10.6 mm × 12.0 mm die and seven metal layer substrates. Although both internal circuits were the same, the metal surface was used for the die corner designed as described above in the BGA side metal layer layout of package A, but package B did not. Further, for package A, a reinforcing material provided with a large opening for providing a die reinforcing material gap of 6.6 mm × 6.9 mm and a lid having a thickness of 0.5 mm was used. For package B, a reinforcing material provided with an opening for providing a die-reinforcing material gap of 2.8 mm × 3.5 mm and a lid having a thickness of 1.0 mm was used. Thus, the four metal surfaces of the present invention were used for package A, but not for package B.

  Samples from both packages were assembled with the die using the same assembly procedure. After assembly, the sample was subjected to 1500 cycles of heat cycle at 125-55 ° C. After thermal cycling, Package A showed no cracks in the BGA side dielectric for the 35 samples examined. On the other hand, in package B, cracks in the die corner were visually observed in 9 out of 35 samples.

  While various embodiments of the invention have been described, these and other embodiments are within the scope of the appended claims. For example, the embodiments of the invention described herein may be used in combination with any of the additional structures or processes described in the following US patents. US Pat. No. 5,888,630, US Pat. No. 6,018,196, US Pat. No. 5,983,974, US Pat. No. 5,836,063, US Pat. US Pat. No. 5,731,047, US Pat. No. 5,841,075, US Pat. No. 5,868,950, US Pat. No. 5,888,631, US Pat. , 900, 312, U.S. Patent 6,011,697, U.S. Patent 6,021,564, U.S. Patent 6,103,992, U.S. Patent 6,127. , 250, U.S. Patent 6,143,401, U.S. Patent 6,183,592, U.S. Patent 6,203,891 and U.S. Patent 6,248,959. Issue statement.

1 is a schematic cross-sectional view of a representative assembled interconnect module. It is the schematic of the crack formation area | region of an interconnection module. FIG. 3 is a schematic view of a crack formation region of an interconnect module, and is an exploded view of the region shown in 2a. It is a schematic sectional drawing of seven metal layer interconnection substrates. It is a schematic sectional drawing of seven metal layer interconnection substrates. It is a schematic sectional drawing which shows the deformation | transformation behavior of the interconnection module in the case of cooling. It is a schematic sectional drawing which shows the deformation | transformation behavior of the interconnection module in the case of cooling. 4 is a graph illustrating fracture toughness as a function of temperature for a microram dielectric material. 3 is a graph showing fatigue behavior of a MICROLAM dielectric material used for an interconnect substrate. 2 is a detailed finite element model geometry of an interconnect substrate. FIG. 4 is a detailed finite element model geometry of the maximum principal strain in the BGA-side dielectric layer of the interconnect substrate around the bond pad. 6 is a graph showing a stress concentration profile around a BGA bond pad. FIG. 4 is a finite element model of the effect of die reinforcement gap size on the relatively desirable size and shape of a solid die corner surface. FIG. 4 is a finite element model of the effect of die reinforcement gap size on the relatively desirable size and shape of a solid die corner surface. FIG. 4 is a finite element model of the effect of die reinforcement gap size on the relatively desirable size and shape of a solid die corner surface. The die corner surface design rules for determining the desired size and position of the solid die corner surface relative to the die corner are shown. The solid surface of the die corner is shown in the form of an unpatterned area on the chip mounting surface. The solid surface of the die corner is shown in the form of an unpatterned area on the chip mounting surface.

Claims (8)

  A substrate having a chip mounting surface and a board mounting surface defining a contact pad for mounting a corresponding pad on the chip and the board, wherein the substrate board mounting surface is near the chip mounting surface area at least one chip corner; A stacked flip chip interconnect package comprising: at least one solid surface overlying the solid surface, wherein the solid surface includes a dielectric material.   The stacked flip chip interconnect package of claim 1, wherein the dielectric material is covered with a layer of material selected from a solder mask and a coverlay material.   The stacked flip chip interconnect package of claim 2, wherein the layer of material is selected from the group consisting of polyimide, polytetrafluoroethylene and expanded polytetrafluoroethylene impregnated with cyanate ester and epoxy.   A substrate having a chip mounting surface and a board mounting surface defining a contact pad for mounting a corresponding pad on the chip and the board, the substrate board surface covering at least the chip mounting surface area near the chip corner A stacked flip chip interconnect package comprising one solid surface, wherein the solid surface comprises metal.   The stacked flip chip interconnect package of claim 4, wherein the metal is selected from the group consisting of copper, silver, gold and aluminum.   The stacked flip chip interconnect package of claim 4, wherein the metal is covered with a layer of material selected from a solder mask and a coverlay material.   The stacked flip chip interconnect package of claim 6, wherein the layer of material is selected from the group consisting of polyimide, polytetrafluoroethylene and expanded polytetrafluoroethylene impregnated with cyanate ester and epoxy. The stacked flip chip interconnect package of claim 4, wherein the solder mask has a plurality of openings defining a ball grid array pad.

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