JP2006501652A - 耐クラック性の相互接続モジュール - Google Patents
耐クラック性の相互接続モジュール Download PDFInfo
- Publication number
- JP2006501652A JP2006501652A JP2004540216A JP2004540216A JP2006501652A JP 2006501652 A JP2006501652 A JP 2006501652A JP 2004540216 A JP2004540216 A JP 2004540216A JP 2004540216 A JP2004540216 A JP 2004540216A JP 2006501652 A JP2006501652 A JP 2006501652A
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- JP
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- Prior art keywords
- chip
- die
- substrate
- dielectric
- mounting surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
1.本明細書で用いる「導電性」という用語は、電気を通すことを意味する。
2.「幾何学的不連続性」という用語は、材料の連続領域を中断する接触パッドや開口部のような特徴部(feature)のことを意味する。
3.本明細書で用いる「相互接続基板」という用語は、「パッケージ基板」、「可撓性パッケージ基板」、「剛性パッケージ基板」等という用語に相当する。
4.「ソリッド面」という用語は、幾何学的不連続性のない単一材料の領域を意味する。
Claims (8)
- チップとボードに、対応するパッドを取付けるための接触パッドを画定するチップ取付け表面とボード取付け表面とを有する基板を含み、前記基板ボード取付け表面が、少なくとも1つのチップコーナー近傍の前記チップ取付け表面領域を覆う少なくとも1つのソリッド面を含み、前記ソリッド面が誘電体材料を含む積層フリップチップ相互接続パッケージ。
- 前記誘電体材料が、はんだマスクおよびカバーレイ材料から選択される材料の層で覆われている、請求項1に記載の積層フリップチップ相互接続パッケージ。
- 前記材料の層が、ポリイミド、ポリテトラフルオロエチレンならびにシアネートエステルおよびエポキシを含浸させた膨張ポリテトラフルオロエチレンからなる群より選択される、請求項2に記載の積層フリップチップ相互接続パッケージ。
- チップとボードに、対応するパッドを取付けるための接触パッドを画定するチップ取付け表面とボード取付け表面とを有する基板を含み、前記基板ボード表面が、前記チップコーナー近傍の前記チップ取付け表面領域を覆う少なくとも1つのソリッド面を含み、前記ソリッド面が金属を含む、積層フリップチップ相互接続パッケージ。
- 前記金属が、銅、銀、金およびアルミニウムからなる群より選択される、請求項4に記載の積層フリップチップ相互接続パッケージ。
- 前記金属が、はんだマスクおよびカバーレイ材料から選択される材料の層で覆われている、請求項4に記載の積層フリップチップ相互接続パッケージ。
- 前記材料の層が、ポリイミド、ポリテトラフルオロエチレンならびにシアネートエステルおよびエポキシを含浸させた膨張ポリテトラフルオロエチレンからなる群より選択される、請求項6に記載の積層フリップチップ相互接続パッケージ。
- 前記はんだマスクが、ボールグリッドアレイパッドを画定する複数の開口部を有している、請求項4に記載の積層フリップチップ相互接続パッケージ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41446102P | 2002-09-27 | 2002-09-27 | |
US10/668,881 US20040104463A1 (en) | 2002-09-27 | 2003-09-23 | Crack resistant interconnect module |
PCT/US2003/030060 WO2004030096A2 (en) | 2002-09-27 | 2003-09-24 | Crack resistant interconnect module |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006501652A true JP2006501652A (ja) | 2006-01-12 |
JP2006501652A5 JP2006501652A5 (ja) | 2006-11-02 |
Family
ID=32045287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004540216A Pending JP2006501652A (ja) | 2002-09-27 | 2003-09-24 | 耐クラック性の相互接続モジュール |
Country Status (8)
Country | Link |
---|---|
US (1) | US20040104463A1 (ja) |
EP (1) | EP1543559A2 (ja) |
JP (1) | JP2006501652A (ja) |
KR (1) | KR20050075340A (ja) |
CN (1) | CN1685505A (ja) |
AU (1) | AU2003275208A1 (ja) |
TW (1) | TW200421563A (ja) |
WO (1) | WO2004030096A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9566361B2 (en) | 2010-03-31 | 2017-02-14 | Incorporated Administrative Agency, National Agriculture And Food Research Organization | Method for catalyzing a fenton reaction |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003298196A (ja) * | 2002-04-03 | 2003-10-17 | Japan Gore Tex Inc | プリント配線板用誘電体フィルム、多層プリント基板および半導体装置 |
DE60233077D1 (de) * | 2002-08-09 | 2009-09-03 | Fujitsu Microelectronics Ltd | Halbleiterbauelement und verfahren zu seiner herstellung |
JP2006120935A (ja) * | 2004-10-22 | 2006-05-11 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
FI20051228L (sv) * | 2005-12-01 | 2007-07-27 | Zipic Oy | Komponentlåda med mikrokrets |
US20090223700A1 (en) * | 2008-03-05 | 2009-09-10 | Honeywell International Inc. | Thin flexible circuits |
KR101184375B1 (ko) * | 2010-05-10 | 2012-09-20 | 매그나칩 반도체 유한회사 | 패드 영역의 크랙 발생을 방지하는 반도체 장치 및 그 제조 방법 |
US20130027894A1 (en) * | 2011-07-27 | 2013-01-31 | Harris Corporation | Stiffness enhancement of electronic substrates using circuit components |
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-
2003
- 2003-09-23 US US10/668,881 patent/US20040104463A1/en not_active Abandoned
- 2003-09-24 CN CNA038227789A patent/CN1685505A/zh active Pending
- 2003-09-24 WO PCT/US2003/030060 patent/WO2004030096A2/en active Application Filing
- 2003-09-24 KR KR1020057005266A patent/KR20050075340A/ko not_active Application Discontinuation
- 2003-09-24 JP JP2004540216A patent/JP2006501652A/ja active Pending
- 2003-09-24 AU AU2003275208A patent/AU2003275208A1/en not_active Abandoned
- 2003-09-24 EP EP03759479A patent/EP1543559A2/en not_active Withdrawn
- 2003-09-26 TW TW092126641A patent/TW200421563A/zh unknown
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9566361B2 (en) | 2010-03-31 | 2017-02-14 | Incorporated Administrative Agency, National Agriculture And Food Research Organization | Method for catalyzing a fenton reaction |
US9566360B2 (en) | 2010-03-31 | 2017-02-14 | Incorporated Administrative Agency National Agriculture And Food Research Organization | Fenton reaction catalyst using coffee grounds or tea dregs as raw material |
Also Published As
Publication number | Publication date |
---|---|
EP1543559A2 (en) | 2005-06-22 |
KR20050075340A (ko) | 2005-07-20 |
WO2004030096A2 (en) | 2004-04-08 |
AU2003275208A8 (en) | 2004-04-19 |
WO2004030096A3 (en) | 2004-06-17 |
US20040104463A1 (en) | 2004-06-03 |
AU2003275208A1 (en) | 2004-04-19 |
CN1685505A (zh) | 2005-10-19 |
TW200421563A (en) | 2004-10-16 |
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Legal Events
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A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060914 |
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