JP2006261485A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2006261485A
JP2006261485A JP2005078581A JP2005078581A JP2006261485A JP 2006261485 A JP2006261485 A JP 2006261485A JP 2005078581 A JP2005078581 A JP 2005078581A JP 2005078581 A JP2005078581 A JP 2005078581A JP 2006261485 A JP2006261485 A JP 2006261485A
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Japan
Prior art keywords
main surface
semiconductor chip
semiconductor device
wiring board
resist film
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JP2005078581A
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English (en)
Japanese (ja)
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JP2006261485A5 (enExample
Inventor
Yoshihiko Shimanuki
好彦 嶋貫
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005078581A priority Critical patent/JP2006261485A/ja
Priority to TW095105294A priority patent/TW200636938A/zh
Priority to CNB2006100586776A priority patent/CN100568498C/zh
Priority to KR1020060024883A priority patent/KR20060101385A/ko
Priority to US11/378,449 priority patent/US7408252B2/en
Publication of JP2006261485A publication Critical patent/JP2006261485A/ja
Publication of JP2006261485A5 publication Critical patent/JP2006261485A5/ja
Priority to US12/147,905 priority patent/US7576422B2/en
Priority to US12/497,174 priority patent/US7803658B2/en
Pending legal-status Critical Current

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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2005078581A 2005-03-18 2005-03-18 半導体装置およびその製造方法 Pending JP2006261485A (ja)

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JP2005078581A JP2006261485A (ja) 2005-03-18 2005-03-18 半導体装置およびその製造方法
TW095105294A TW200636938A (en) 2005-03-18 2006-02-16 A semiconductor device and a manufacturing method of the same
CNB2006100586776A CN100568498C (zh) 2005-03-18 2006-03-08 半导体器件及其制造方法
KR1020060024883A KR20060101385A (ko) 2005-03-18 2006-03-17 반도체 장치 및 그 제조 방법
US11/378,449 US7408252B2 (en) 2005-03-18 2006-03-20 Semiconductor device and a manufacturing method of the same
US12/147,905 US7576422B2 (en) 2005-03-18 2008-06-27 Semiconductor device
US12/497,174 US7803658B2 (en) 2005-03-18 2009-07-02 Semiconductor device

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JP2008288400A (ja) * 2007-05-18 2008-11-27 Panasonic Corp 回路基板，樹脂封止型半導体装置，樹脂封止型半導体装置の製造方法，トレイおよび検査ソケット
US8357998B2 (en) * 2009-02-09 2013-01-22 Advanced Semiconductor Engineering, Inc. Wirebonded semiconductor package
TWI388018B (zh) * 2009-10-22 2013-03-01 欣興電子股份有限公司 封裝結構之製法
TWI416636B (zh) * 2009-10-22 2013-11-21 欣興電子股份有限公司 封裝結構之製法
CN102054714B (zh) * 2009-11-06 2012-10-03 欣兴电子股份有限公司 封装结构的制法
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
JP2012033637A (ja) 2010-07-29 2012-02-16 Nitto Denko Corp ダイシングテープ一体型半導体裏面用フィルム及び半導体装置の製造方法
US9406579B2 (en) * 2012-05-14 2016-08-02 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage in semiconductor package
CN110429036A (zh) * 2019-06-19 2019-11-08 惠州市志金电子科技有限公司 接触式身份识别卡的封装工艺及接触式身份识别卡
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法

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CN1835222A (zh) 2006-09-20
US7803658B2 (en) 2010-09-28
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KR20060101385A (ko) 2006-09-22
US20080258312A1 (en) 2008-10-23

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