CN100568498C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN100568498C
CN100568498C CNB2006100586776A CN200610058677A CN100568498C CN 100568498 C CN100568498 C CN 100568498C CN B2006100586776 A CNB2006100586776 A CN B2006100586776A CN 200610058677 A CN200610058677 A CN 200610058677A CN 100568498 C CN100568498 C CN 100568498C
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China
Prior art keywords
semiconductor chip
resist film
wiring board
printed wiring
dry type
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Expired - Fee Related
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CNB2006100586776A
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English (en)
Chinese (zh)
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CN1835222A (zh
Inventor
岛贯好彦
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Renesas Electronics Corp
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Renesas Technology Corp
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Publication of CN1835222A publication Critical patent/CN1835222A/zh
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
CNB2006100586776A 2005-03-18 2006-03-08 半导体器件及其制造方法 Expired - Fee Related CN100568498C (zh)

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JP2007335581A (ja) * 2006-06-14 2007-12-27 Renesas Technology Corp 半導体装置の製造方法
JP2008288400A (ja) * 2007-05-18 2008-11-27 Panasonic Corp 回路基板，樹脂封止型半導体装置，樹脂封止型半導体装置の製造方法，トレイおよび検査ソケット
US8357998B2 (en) * 2009-02-09 2013-01-22 Advanced Semiconductor Engineering, Inc. Wirebonded semiconductor package
JP2010278306A (ja) * 2009-05-29 2010-12-09 Sanyo Electric Co Ltd 半導体装置
TWI388018B (zh) * 2009-10-22 2013-03-01 欣興電子股份有限公司 封裝結構之製法
TWI416636B (zh) * 2009-10-22 2013-11-21 欣興電子股份有限公司 封裝結構之製法
CN102054714B (zh) * 2009-11-06 2012-10-03 欣兴电子股份有限公司 封装结构的制法
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
JP2012033637A (ja) 2010-07-29 2012-02-16 Nitto Denko Corp ダイシングテープ一体型半導体裏面用フィルム及び半導体装置の製造方法
US9406579B2 (en) * 2012-05-14 2016-08-02 STATS ChipPAC Pte. Ltd. Semiconductor device and method of controlling warpage in semiconductor package
CN110429036A (zh) * 2019-06-19 2019-11-08 惠州市志金电子科技有限公司 接触式身份识别卡的封装工艺及接触式身份识别卡
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法

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DE3408630A1 (de) * 1984-03-09 1985-09-12 Hoechst Ag, 6230 Frankfurt Verfahren und schichtmaterial zur herstellung durchkontaktierter elektrischer leiterplatten
JP2001284491A (ja) * 2000-03-31 2001-10-12 Sumitomo Metal Electronics Devices Inc プラスチック基板
JP2004152778A (ja) * 2001-09-05 2004-05-27 Hitachi Chem Co Ltd 半導体搭載用基板とその製造方法とそれを用いた半導体パッケージ並びにその製造方法
JP4963148B2 (ja) 2001-09-18 2012-06-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7579251B2 (en) * 2003-05-15 2009-08-25 Fujitsu Limited Aerosol deposition process
JP4260617B2 (ja) * 2003-12-24 2009-04-30 株式会社ルネサステクノロジ 半導体装置の製造方法
US7489032B2 (en) * 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
JP2005277356A (ja) * 2004-03-26 2005-10-06 Sanyo Electric Co Ltd 回路装置
KR100557540B1 (ko) * 2004-07-26 2006-03-03 삼성전기주식회사 Ｂｇａ 패키지 기판 및 그 제작 방법

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