JP2006210596A - 半導体装置およびその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 title description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 119
- 239000013078 crystal Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 238000009792 diffusion process Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- -1 HfO 2 Chemical class 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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Abstract
【解決手段】 下層に無歪みSiGe混晶層を有する歪みSiチャネル層上にpチャネルMOSトランジスタを形成する際に、チャネル領域の両側に、無歪みSiGe混晶層からエピタキシャルにSiGe混晶領域を成長させ、前記歪みSiチャネル層をかかるSiGe混晶層領域に格子整合させることにより、歪みSiチャネル層中における応力緩和を阻止し、効率的な応力印加を実現する。
【選択図】 図11
Description
図5は、本発明で使う、歪みSOI(silicon-on-insulator)基板20の構成を、図6(A)〜(C)は、その製造方法を示す。
[第2実施形態]
図13は、本発明の第2の実施形態によるpチャネルMOSトランジスタの構成を示す。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
1A,1B SiGe混晶領域
1a,1b,41C,41D ソース/ドレイン拡散領域
2,42 ゲート絶縁膜
3,43 ゲート電極
3A,3B,43A,43B 側壁絶縁膜
11,23,33 無歪みSiGe層
12,25 歪みSi層
14,24 絶縁層
23,32 SiGe組成傾斜層
23A,23B,33A,33B SiGe混晶領域
24A,24B 開口部
33I STI領域
40 pチャネルMOSトランジスタ
40A 素子領域
41A,41B ソース/ドレインエクステンション領域
43a,43b CVD酸化膜
Claims (9)
- SiGe混晶層と、前記SiGe混晶層上に絶縁膜を介して形成された歪みSi層とよりなり、前記歪みSi層中にはチャネル領域が形成される歪みSOI基板と、
前記歪みSi層上に、前記チャネル領域に対応して、ゲート絶縁膜を介して形成されたゲート電極と、
前記歪みSi層中、前記チャネル領域のそれぞれ第1および第2の側に形成された第1および第2のp型拡散領域とよりなるpチャネルMOSトランジスタであって、
前記前記歪みSi層は、前記第1および第2の側に、それぞれ第1および第2の側壁面を有し、
前記第1の側壁面に接して、前記SiGe混晶層に対してエピタキシャルに形成された第1のSiGe混晶領域が形成されており、
前記第2の側壁面に接して、前記SiGe混晶層に対してエピタキシャルに形成された第2のSiGe混晶領域が形成されており、
前記第1および第2のSiGe混晶領域は、前記歪みSi層に対して、それぞれ前記第1および第2の側壁面において格子整合していることを特徴とするpチャネルMOSトランジスタ。 - SiGe混晶層上にエピタキシャルに形成された歪みSi層を含み、前記歪みSi層中にはチャネル領域が形成される歪みシリコン基板と、
前記歪みSi層上に、前記チャネル領域に対応して、ゲート絶縁膜を介して形成されたゲート電極と、
前記歪みSi層中、前記チャネル領域のそれぞれ第1および第2の側に形成された第1および第2のp型拡散領域とよりなるpチャネルMOSトランジスタであって、
前記前記歪みSi層は、前記第1および第2の側に、それぞれ第1および第2の側壁面を有し、
前記第1の側壁面に接して、前記SiGe混晶層に対してエピタキシャルに形成された第1のSiGe混晶領域が形成されており、
前記第2の側壁面に接して、前記SiGe混晶層に対してエピタキシャルに形成された第2のSiGe混晶領域が形成されており、
前記第1および第2のSiGe混晶領域は、前記歪みSi層に対して、それぞれ前記第1および第2の側壁面において格子整合していることを特徴とするpチャネルMOSトランジスタ。 - 前記歪みSi層は、前記歪みSi層の面内に作用する面内引張り応力を蓄積しており、さらに前記歪みSi層の面に垂直方向に作用する一軸引張り応力を蓄積していることを特徴とする請求項1または2記載のpチャネルMOSトランジスタ。
- 前記第1および第2のSiGe混晶領域の各々は、少なくとも前記歪みSi層の表面にまで到達するように形成されていることを特徴とする請求項1〜3のうち、いずれか一項記載のpチャネルMOSトランジスタ。
- 前記第1および第2のSiGe混晶領域では、その上部にp型拡散領域が、それぞれソースおよびドレイン領域として形成されていることを特徴とする請求項1〜4のうち、いずれか一項記載のpチャネルMOSトランジスタ。
- 前記SiGe混晶層は、少なくともその上部が実質的な歪みを有さないことを特徴とする請求項1〜5のうち、いずれか一項記載のpチャネルMOSトランジスタ。
- 前記SiGe混晶層は、シリコン基板上にエピタキシャルに形成されていることを特徴とする請求項1〜5のうち、いずれか一項記載のpチャネルMOSトランジスタ。
- SiGe混晶層と、前記SiGe混晶層上に絶縁膜を介して形成された歪みSi層とよりなり、前記歪みSi層中にはチャネル領域が形成される歪みSOI基板と、前記歪みSi層上に、前記チャネル領域に対応して、ゲート絶縁膜を介して形成されたゲート電極と、前記歪みSi層中、前記チャネル領域のそれぞれ第1および第2の側に形成された第1および第2のp型拡散領域とよりなるpチャネルMOSトランジスタの製造方法であって、
前記前記歪みSi層中、前記第1および第2の側に、前記SiGe混晶層が露出するように、それぞれ第1および第2の側壁面で画成された第1および第2の開口部を形成する工程と、
前記第1および第2の開口部において、それぞれ第1および第2の側壁面に接するように、第1および第2のSiGe混晶層領域をエピタキシャルに成長させる工程と
を含むことを特徴とするpチャネルMOSトランジスタの製造方法。 - SiGe混晶層と、前記SiGe混晶層上にエピタキシャルに形成された歪みSi層とよりなり、前記歪みSi層中にはチャネル領域が形成される歪みシリコン基板と、前記歪みSi層上に、前記チャネル領域に対応して、ゲート絶縁膜を介して形成されたゲート電極と、前記歪みSi層中、前記チャネル領域のそれぞれ第1および第2の側に形成された第1および第2のp型拡散領域とよりなるpチャネルMOSトランジスタの製造方法であって、
前記前記歪みSi層中、前記第1および第2の側に、前記SiGe混晶層が露出するように、それぞれ第1および第2の側壁面で画成された第1および第2の開口部を形成する工程と、
前記第1および第2の開口部において、それぞれ第1および第2の側壁面に接するように、第1および第2のSiGe混晶層領域をエピタキシャルに成長させる工程と
を含むことを特徴とするpチャネルMOSトランジスタの製造方法。
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JP2005019855A JP4481181B2 (ja) | 2005-01-27 | 2005-01-27 | 半導体装置およびその製造方法 |
US11/114,047 US7262465B2 (en) | 2005-01-27 | 2005-04-26 | P-channel MOS transistor and fabrication process thereof |
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KR20160111495A (ko) * | 2014-01-23 | 2016-09-26 | 썬에디슨 세미컨덕터 리미티드 | 고 비저항 soi 웨이퍼 및 그 제조 방법 |
JP2017532781A (ja) * | 2014-09-18 | 2017-11-02 | ソイテックSoitec | 異なる歪み状態を有するトランジスタチャネルを含む半導体層を製作する方法及び関連半導体層 |
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JP4369359B2 (ja) * | 2004-12-28 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
US8294224B2 (en) * | 2006-04-06 | 2012-10-23 | Micron Technology, Inc. | Devices and methods to improve carrier mobility |
US7538387B2 (en) * | 2006-12-29 | 2009-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stack SiGe for short channel improvement |
US7994062B2 (en) * | 2009-10-30 | 2011-08-09 | Sachem, Inc. | Selective silicon etch process |
JP2011199132A (ja) * | 2010-03-23 | 2011-10-06 | Sumitomo Electric Ind Ltd | 半導体装置およびその製造方法 |
DE102010064290B3 (de) * | 2010-12-28 | 2012-04-19 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verformungserhöhung in Transistoren mit einem eingebetteten verformungsinduzierenden Halbleitermaterial durch Kondensation der legierungsbildenden Substanz |
FR2986369B1 (fr) * | 2012-01-30 | 2016-12-02 | Commissariat Energie Atomique | Procede pour contraindre un motif mince et procede de fabrication de transistor integrant ledit procede |
US9570609B2 (en) | 2013-11-01 | 2017-02-14 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same |
US9484423B2 (en) | 2013-11-01 | 2016-11-01 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet III-V channel FETs |
US9647098B2 (en) | 2014-07-21 | 2017-05-09 | Samsung Electronics Co., Ltd. | Thermionically-overdriven tunnel FETs and methods of fabricating the same |
FR3025941A1 (fr) * | 2014-09-17 | 2016-03-18 | Commissariat Energie Atomique | Transistor mos a resistance et capacites parasites reduites |
US9219150B1 (en) | 2014-09-18 | 2015-12-22 | Soitec | Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures |
KR101852424B1 (ko) | 2016-10-07 | 2018-04-27 | 재단법인 다차원 스마트 아이티 융합시스템 연구단 | 무접합 트랜지스터의 구동전류를 증가시키는 방법 |
CN113471214B (zh) * | 2021-05-18 | 2023-09-19 | 中国科学院微电子研究所 | 一种多层绝缘体上硅锗衬底结构及其制备方法和用途 |
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US20060163557A1 (en) | 2006-07-27 |
US7262465B2 (en) | 2007-08-28 |
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