JP2017532781A - 異なる歪み状態を有するトランジスタチャネルを含む半導体層を製作する方法及び関連半導体層 - Google Patents
異なる歪み状態を有するトランジスタチャネルを含む半導体層を製作する方法及び関連半導体層 Download PDFInfo
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- JP2017532781A JP2017532781A JP2017514528A JP2017514528A JP2017532781A JP 2017532781 A JP2017532781 A JP 2017532781A JP 2017514528 A JP2017514528 A JP 2017514528A JP 2017514528 A JP2017514528 A JP 2017514528A JP 2017532781 A JP2017532781 A JP 2017532781A
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Abstract
Description
半導体構造体を形成する方法であって、半導体オンインシュレータ(SOI)基板を用意することであって、SOI基板が、ベース基板と、結晶学的歪み材料を含むベース基板より上のストレッサ層と、表面半導体層と、ストレッサ層と表面半導体層との間に配置される誘電体層とを含む、半導体オンインシュレータ(SOI)基板を用意することと、イオンをストレッサ層の少なくとも第2の領域の中に注入することなく、又は第2の領域を貫通して注入することなく、イオンをストレッサ層の少なくとも第1の領域の中に注入する、又は第1の領域を貫通して注入することと、追加的な半導体材料をストレッサ層の少なくとも第1の領域より上の表面半導体層上に形成することと、ストレッサ層の少なくとも第1の領域より上の表面半導体層の第1の領域の歪み状態を変化させることと、表面半導体層を貫通してベース基板の少なくとも一部の中に入るトレンチ構造体を形成することと、ストレッサ層の少なくとも第2の領域より上の表面半導体層の第2の領域の歪み状態を変化させることとを含む。
実施形態1の方法であって、ストレッサ層の少なくとも第2の領域より上の表面半導体層の第2の領域の歪み状態を変化させることは、表面半導体層の第2の領域の歪み状態を、表面半導体層の第1の領域の歪み状態とは異なるようにさせることを含む。
実施形態1又は実施形態2の方法であって、表面半導体層の第1の領域の歪み状態を変化させることは、表面半導体層の第1の領域の圧縮歪みを誘発することを含む。
実施形態1〜3のいずれか1つの方法であって、表面半導体層の第2の領域の歪み状態を変化させることは、表面半導体層の第2の領域の引張歪みを誘発することを含む。
実施形態1〜4のいずれか1つの方法であって、用意されたSOI基板のストレッサ層は、少なくとも1ギガパスカルの圧縮応力を有する。
実施形態1〜5のいずれか1つの方法であって、用意されたSOI基板のストレッサ層は、圧縮歪みSixGe1−x層を備える。
実施形態6の方法であって、SOI基板を用意することは、歪みSixGe1−x層をベース基板上にエピタキシャルに堆積することを更に含み、歪みSixGe1−x層が、ストレッサ層を形成する。
実施形態7の方法であって、歪みSixGe1−x層をベース基板上にエピタキシャルに堆積することは、歪みSixGe1−x層をベース基板上に擬似形態的に堆積することを更に含む。
実施形態7の方法であって、歪みSixGe1−x層をベース基板上にエピタキシャルに堆積することは、歪みSixGe1−x層をベース基板上に非擬似形態的に堆積することを更に含む。
実施形態7〜9のいずれか1つの方法であって、約0.15〜約1.00の間のゲルマニウム組成物(x)を有するように歪みSixGe1−x層を形成することを更に含む。
実施形態10の方法であって、約0.20〜約0.60の間のゲルマニウム組成物(x)を有するように歪みSixGe1−x層を形成することを更に含む。
実施形態7〜11のいずれか1つの方法であって、歪みSixGe1−x層をベース基板上にエピタキシャルに堆積することは、約10ナノメータ〜約50ナノメータの間の厚さを有するように歪みSixGe1−x層を形成することを更に含む。
実施形態7〜12のいずれか1つの方法であって、イオンをストレッサ層の少なくとも第1の領域の中に注入すること、又は少なくとも第1の領域を貫通して注入することは、歪みSixGe1−x層の歪みを緩和して、実質的な歪み緩和SixGe1−xを形成することを更に含む。
実施形態1〜13のいずれか1つの方法であって、用意されたSOI基板の誘電体層は、1つ又は複数の誘電体層を備え、各誘電体層は、窒化珪素、酸化珪素、及び酸窒化珪素で構成される群から選択された材料を含む。
実施形態1〜14のいずれか1つの方法であって、用意されたSOI基板の誘電体層は、ほぼ50nm以下の厚さを有する。
実施形態1〜15のいずれか1つの方法であって、イオンをストレッサ層の少なくとも一部の中に注入する、又はストレッサ層の少なくとも一部を貫通して注入することは、ゲルマニウム、珪素、炭素、アルゴン、及び不活性ガスイオンのうちの1つ又は複数をストレッサ層の少なくとも一部の中に注入する、又はストレッサ層の少なくとも一部を貫通して注入することを含む。
実施形態1〜16のいずれか1つの方法であって、イオンをストレッサ層の少なくとも第2の領域の中に注入することなく、又は少なくとも第2の領域を貫通して注入することなく、イオンをストレッサ層の少なくとも第1の領域の中に注入する、又は少なくとも第1の領域を貫通して注入することは、パターン付きマスク層を表面半導体層の上に設けることと、イオンを、パターン付きマスク層を貫通させてから、ストレッサ層の少なくとも第1の領域の中に注入する又はストレッサ層の少なくとも第1の領域を貫通して注入することとを含む。
実施形態1〜17のいずれか1つの方法であって、追加的な半導体材料をストレッサ層の第1の領域より上の表面半導体層上に形成することは、Si1−xGexを表面半導体層上にエピタキシャルに堆積することを更に含み、Si1−xGexが、追加的な半導体材料を形成する。
実施形態18の方法であって、Si1−xGexを表面半導体層上にエピタキシャルに堆積することは、約0.10〜約0.30の間のゲルマニウム組成物(x)を有するSi1−xGexを堆積することを含む。
実施形態1〜19のいずれか1つの方法であって、ストレッサ層の少なくとも第1の領域より上の表面半導体層の第1の領域の歪み状態を変化させることは、表面半導体層の第1の領域の拡散された元素の濃度を上昇させるように、追加的な半導体材料から表面半導体層の第1の領域の中に元素を拡散させることを更に含む。
実施形態20の方法であって、表面半導体層の第1の領域の拡散された元素の濃度を上昇させるように、追加的な半導体材料から表面半導体層の第1の領域の中に元素を拡散させることは、追加的な半導体材料から表面半導体層の第1の領域の中にゲルマニウムを拡散させることを更に含む。
実施形態20又は実施形態21の方法であって、追加的な半導体材料から表面半導体層の第1の領域の中に元素を拡散させることは、凝縮プロセスを実行することを含む。
実施形態22の方法であって、凝縮プロセスを実行することは、追加的な半導体材料の一部を酸化させることを含む。
実施形態1〜23のいずれか1つの方法であって、トレンチ構造体を誘電体分離材料で充填することを更に含む。
実施形態1〜24のいずれか1つの方法であって、表面半導体層の第1の領域に少なくとも1つのPMOSデバイス構造体を形成することを更に含む。
実施形態1〜25のいずれか1つの方法であって、表面半導体層の第2の領域に少なくとも1つのNMOSデバイス構造体を形成することを更に含む。
半導体構造体は、ベース基板と、ベース基板より上の少なくとも第1の領域及び第2の領域とを備え、第1の領域が、ベース基板上に配置された実質的な緩和層と、ベース基板と反対の実質的な緩和層の側で実質的な緩和層より上に配置された誘電体層と、誘電体層より上に配置された圧縮歪み表面半導体層とを含み、第2の領域が、ベース基板上に配置された圧縮歪み層と、ベース基板と反対の側で圧縮歪み層より上に配置された誘電体層と、誘電体層より上に配置された引張歪み表面半導体層とを備え、第1の領域及び第2の領域が、誘電体分離材料によって互いに横方向に分離されている。
実施形態27の半導体構造体であって、ベース基板が、珪素ベース基板を備える。
実施形態27又は実施形態28の半導体構造体であって、第1の領域の実質的な緩和層が、その中に注入されたイオンを備える。
実施形態27〜29のいずれか1つの半導体構造体であって、第1の領域の実質的な緩和層が、実質的な緩和Si1−xGex層を備える。
実施形態30の半導体構造体であって、実質的な緩和Si1−xGex層が、約0.15〜約0.60の間のゲルマニウム組成物(x)を有する。
実施形態27〜31のいずれか1つの半導体構造体であって、第1の領域の圧縮歪み表面半導体層が、圧縮歪みSi1−yGey層を備える。
実施形態32の半導体構造体であって、圧縮歪みSi1−yGey層が、約0.10〜約0.30の間のゲルマニウム組成物(y)を有する。
実施形態32又は実施形態33の半導体構造体であって、圧縮歪みSi1−yGey層が、少なくとも1ギガパスカルの圧縮歪みを有する。
実施形態32〜34のいずれか1つの半導体構造体であって、圧縮歪みSi1−yGey層が、ほぼ1×104cm−2以下の欠陥密度を有する。
実施形態32〜35のいずれか1つの半導体構造体であって、圧縮歪みSi1−yGey層に形成された少なくとも1つのデバイス構造体を更に備える。
実施形態27〜36のいずれか1つの半導体構造体であって、第2の領域の圧縮歪み層が、圧縮歪みSi1−xGex層を備える。
実施形態37の半導体構造体であって、圧縮歪みSi1−xGex層が、約0.15〜約0.30の間のゲルマニウム組成物(x)を有する。
実施形態27〜38のいずれか1つの半導体構造体であって、第2の領域の引張歪み表面半導体層が、引張歪み珪素層を備える。
実施形態39の半導体構造体であって、引張歪みシリコン層が、少なくとも1ギガパスカルの引張歪みを有する。
実施形態39又は実施形態40の半導体構造体であって、引張歪み珪素層が、ほぼ1×104cm−2以下の欠陥密度を有する。
実施形態39〜41のいずれか1つの半導体構造体であって、引張歪み珪素層に形成された少なくとも1つのデバイス構造体を更に備える。
Claims (15)
- 半導体構造体を形成する方法であって、
半導体オンインシュレータ(SOI)基板を用意するステップであって、前記SOI基板が、
ベース基板と、
結晶学的歪み材料を含むベース基板より上のストレッサ層と、
表面半導体層と、
前記ストレッサ層と前記表面半導体層との間に配置される誘電体層とを含む、半導体オンインシュレータ(SOI)基板を用意するステップと、
イオンを前記ストレッサ層の少なくとも第2の領域の中に注入することなく、又は少なくとも第2の領域を貫通して注入することなく、イオンを前記ストレッサ層の少なくとも第1の領域の中に注入する、又は少なくとも第1の領域を貫通して注入するステップと、
追加的な半導体材料を前記ストレッサ層の前記少なくとも第1の領域より上の前記表面半導体層上に形成するステップと、
前記ストレッサ層の前記少なくとも第1の領域より上の前記表面半導体層の第1の領域の歪み状態を変化させるステップと、
前記表面半導体層を貫通して前記ベース基板の少なくとも一部の中に入るトレンチ構造体を形成するステップと、
前記ストレッサ層の前記少なくとも第2の領域より上の前記表面半導体層の第2の領域の歪み状態を変化させるステップとを含む、方法。 - 前記ストレッサ層の前記少なくとも第2の領域より上の前記表面半導体層の前記第2の領域の前記歪み状態を変化させるステップが、前記表面半導体層の前記第2の領域の前記歪み状態を、前記表面半導体層の前記第1の領域の前記歪み状態とは異なるようにさせることを含む、請求項1に記載の方法。
- 前記表面半導体層の前記第1の領域の前記歪み状態を変化させるステップが、前記表面半導体層の前記第1の領域の圧縮歪みを誘発することを含む、請求項1に記載の方法。
- 前記表面半導体層の前記第2の領域の前記歪み状態を変化させるステップが、前記表面半導体層の前記第2の領域の引張歪みを誘発することを含む、請求項1に記載の方法。
- 前記用意されたSOI基板の前記ストレッサ層が、圧縮歪みSixGe1−x層を備える、請求項1に記載の方法。
- 前記用意されたSOI基板の前記誘電体層が、1つ又は複数の誘電体層を備え、各誘電体層が、窒化珪素、酸化珪素、及び酸窒化珪素からなる群から選択された材料を備える、請求項1に記載の方法。
- イオンを前記ストレッサ層の少なくとも一部の中に注入するステップ、又は前記ストレッサ層の少なくとも一部を貫通して注入するステップが、ゲルマニウム、珪素、炭素、アルゴン、及び不活性ガスイオンのうちの1つ又は複数を前記ストレッサ層の前記少なくとも一部の中に注入する、又は前記ストレッサ層の前記少なくとも一部を貫通して注入することを含む、請求項1に記載の方法。
- 追加的な半導体材料を前記ストレッサ層の前記第1の領域より上の前記表面半導体層上に形成するステップが、Si1−xGexを前記表面半導体層上にエピタキシャルに堆積することを更に含み、前記Si1−xGexが、前記追加的な半導体材料を形成する、請求項1に記載の方法。
- 前記ストレッサ層の前記少なくとも第1の領域より上の前記表面半導体層の第1の領域の歪み状態を変化させるステップが、前記表面半導体層の前記第1の領域の拡散された元素の濃度を上昇させるように、前記追加的な半導体材料から前記表面半導体層の前記第1の領域の中に前記元素を拡散させることを更に含む、請求項1に記載の方法。
- ベース基板と、
前記ベース基板より上の少なくとも第1の領域及び第2の領域とを備える半導体構造体であって、
前記第1の領域が、
前記ベース基板上に配置された実質的な緩和層と、
前記ベース基板と反対の前記実質的な緩和層の側で前記実質的な緩和層より上に配置された誘電体層と、
前記誘電体層より上に配置された圧縮歪み表面半導体層とを含み、
前記第2の領域が、
前記ベース基板上に配置された圧縮歪み層と、
前記ベース基板と反対の側で前記圧縮歪み層より上に配置された誘電体層と、
前記誘電体層より上に配置された引張歪み表面半導体層とを含み、
前記第1の領域及び前記第2の領域が、誘電体分離材料によって互いに横方向に分離されている、半導体構造体。 - 前記第1の領域の前記実質的な緩和層が、実質的な緩和Si1−xGex層を備える、請求項10に記載の半導体構造体。
- 前記第1の領域の前記圧縮歪み表面半導体層が、圧縮歪みSi1−yGey層を備える、請求項10に記載の半導体構造体。
- 前記第2の領域の前記圧縮歪み層が、圧縮歪みSi1−xGex層を備える、請求項10に記載の半導体構造体。
- 前記第2の領域の前記引張歪み表面半導体層が、引張歪み珪素層を備える、請求項10に記載の半導体構造体。
- 前記引張歪み珪素層に形成された少なくとも1つのデバイス構造体を更に備える、請求項14に記載の半導体構造体。
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170323973A1 (en) * | 2010-08-27 | 2017-11-09 | Acorn Technologies, Inc. | Soi wafers and devices with buried stressor |
US10833194B2 (en) | 2010-08-27 | 2020-11-10 | Acorn Semi, Llc | SOI wafers and devices with buried stressor |
CN103811344B (zh) * | 2012-11-09 | 2016-08-10 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US9219150B1 (en) | 2014-09-18 | 2015-12-22 | Soitec | Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures |
US9559120B2 (en) | 2015-07-02 | 2017-01-31 | International Business Machines Corporation | Porous silicon relaxation medium for dislocation free CMOS devices |
US9443873B1 (en) * | 2015-12-14 | 2016-09-13 | International Business Machines Corporation | Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step |
TWI605552B (zh) | 2016-12-08 | 2017-11-11 | 新唐科技股份有限公司 | 半導體元件、半導體基底及其形成方法 |
US20180212056A1 (en) * | 2017-01-23 | 2018-07-26 | Acorn Technologies, Inc. | Strained semiconductor-on-insulator by deformation of buried insulator induced by buried stressor |
FR3066318B1 (fr) * | 2017-05-12 | 2019-07-12 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Puce a transistors nmos et pmos contraints |
US10192779B1 (en) * | 2018-03-26 | 2019-01-29 | Globalfoundries Inc. | Bulk substrates with a self-aligned buried polycrystalline layer |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10149962A (ja) * | 1996-10-17 | 1998-06-02 | Samsung Electron Co Ltd | 半導体基板およびその製造方法 |
JP2005072464A (ja) * | 2003-08-27 | 2005-03-17 | Sharp Corp | 半導体基板の製造方法および半導体装置の製造方法 |
JP2006210596A (ja) * | 2005-01-27 | 2006-08-10 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2006339243A (ja) * | 2005-05-31 | 2006-12-14 | Toshiba Corp | 半導体装置 |
JP2007088158A (ja) * | 2005-09-21 | 2007-04-05 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2007335573A (ja) * | 2006-06-14 | 2007-12-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2008525998A (ja) * | 2004-12-16 | 2008-07-17 | ウイスコンシン アラムニ リサーチ ファンデーション | ひずみヘテロ接合構造体の製造 |
JP2008172234A (ja) * | 2007-01-12 | 2008-07-24 | Internatl Business Mach Corp <Ibm> | 高性能cmos技術のための低コストの歪みsoi基板 |
JP2010010473A (ja) * | 2008-06-27 | 2010-01-14 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2010527140A (ja) * | 2007-02-12 | 2010-08-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電界効果トランジスタ(FET)の製造方法、n型およびp型電界効果トランジスタ |
JP2010183065A (ja) * | 2009-01-07 | 2010-08-19 | Fujitsu Ltd | 半導体およびその製造方法 |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US6399970B2 (en) | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
FR2755537B1 (fr) | 1996-11-05 | 1999-03-05 | Commissariat Energie Atomique | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
FR2767416B1 (fr) | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2795865B1 (fr) | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'un film mince utilisant une mise sous pression |
FR2809867B1 (fr) | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
FR2818010B1 (fr) | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
JP4796771B2 (ja) * | 2002-10-22 | 2011-10-19 | 台湾積體電路製造股▲ふん▼有限公司 | 半導体デバイス |
US7018909B2 (en) | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
US6963078B2 (en) * | 2003-03-15 | 2005-11-08 | International Business Machines Corporation | Dual strain-state SiGe layers for microelectronics |
US6882025B2 (en) * | 2003-04-25 | 2005-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained-channel transistor and methods of manufacture |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
US7538010B2 (en) | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US7084460B2 (en) * | 2003-11-03 | 2006-08-01 | International Business Machines Corporation | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
US20060113603A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
US7282402B2 (en) * | 2005-03-30 | 2007-10-16 | Freescale Semiconductor, Inc. | Method of making a dual strained channel semiconductor device |
JP2009503907A (ja) * | 2005-08-03 | 2009-01-29 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | 結晶化度が改善された歪シリコン層を有する歪シリコンオンインシュレータ(ssoi)構造 |
DE102005052357A1 (de) | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
JP2007180402A (ja) * | 2005-12-28 | 2007-07-12 | Toshiba Corp | 半導体装置及びその製造方法 |
US7468313B2 (en) | 2006-05-30 | 2008-12-23 | Freescale Semiconductor, Inc. | Engineering strain in thick strained-SOI substrates |
US8962447B2 (en) | 2006-08-03 | 2015-02-24 | Micron Technology, Inc. | Bonded strained semiconductor with a desired surface orientation and conductance direction |
US20080179636A1 (en) * | 2007-01-27 | 2008-07-31 | International Business Machines Corporation | N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers |
DE102007030054B4 (de) * | 2007-06-29 | 2009-04-16 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit reduziertem Gatewiderstand und verbesserter Verspannungsübertragungseffizienz und Verfahren zur Herstellung desselben |
JP2009212413A (ja) * | 2008-03-06 | 2009-09-17 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
US7524740B1 (en) | 2008-04-24 | 2009-04-28 | International Business Machines Corporation | Localized strain relaxation for strained Si directly on insulator |
US8003454B2 (en) * | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
EP2151852B1 (en) | 2008-08-06 | 2020-01-15 | Soitec | Relaxation and transfer of strained layers |
KR101233105B1 (ko) | 2008-08-27 | 2013-02-15 | 소이텍 | 선택되거나 제어된 격자 파라미터들을 갖는 반도체 물질층들을 이용하여 반도체 구조물들 또는 소자들을 제조하는 방법 |
US8169025B2 (en) | 2010-01-19 | 2012-05-01 | International Business Machines Corporation | Strained CMOS device, circuit and method of fabrication |
US8395213B2 (en) * | 2010-08-27 | 2013-03-12 | Acorn Technologies, Inc. | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer |
US8124470B1 (en) * | 2010-09-29 | 2012-02-28 | International Business Machines Corporation | Strained thin body semiconductor-on-insulator substrate and device |
CN102881694A (zh) * | 2011-07-14 | 2013-01-16 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US20130277747A1 (en) * | 2012-04-24 | 2013-10-24 | Stmicroelectronics, Inc. | Transistor having a stressed body |
EP2682983B1 (en) * | 2012-07-03 | 2016-08-31 | Imec | CMOS device comprising silicon and germanium and method for manufacturing thereof |
US8653599B1 (en) | 2012-11-16 | 2014-02-18 | International Business Machines Corporation | Strained SiGe nanowire having (111)-oriented sidewalls |
US8927363B2 (en) * | 2013-05-17 | 2015-01-06 | International Business Machines Corporation | Integrating channel SiGe into pFET structures |
US9165945B1 (en) | 2014-09-18 | 2015-10-20 | Soitec | Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures |
-
2014
- 2014-09-18 US US14/489,841 patent/US9209301B1/en active Active
-
2015
- 2015-08-28 CN CN201580050312.6A patent/CN106716621B/zh active Active
- 2015-08-28 WO PCT/IB2015/001495 patent/WO2016042375A1/en active Application Filing
- 2015-08-28 EP EP15767244.5A patent/EP3195354B1/en active Active
- 2015-08-28 JP JP2017514528A patent/JP6432090B2/ja active Active
- 2015-08-28 SG SG11201702013WA patent/SG11201702013WA/en unknown
- 2015-08-28 KR KR1020177009442A patent/KR101904114B1/ko active IP Right Grant
- 2015-08-31 TW TW104128678A patent/TWI667696B/zh active
- 2015-11-06 US US14/934,567 patent/US9576798B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10149962A (ja) * | 1996-10-17 | 1998-06-02 | Samsung Electron Co Ltd | 半導体基板およびその製造方法 |
JP2005072464A (ja) * | 2003-08-27 | 2005-03-17 | Sharp Corp | 半導体基板の製造方法および半導体装置の製造方法 |
JP2008525998A (ja) * | 2004-12-16 | 2008-07-17 | ウイスコンシン アラムニ リサーチ ファンデーション | ひずみヘテロ接合構造体の製造 |
JP2006210596A (ja) * | 2005-01-27 | 2006-08-10 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2006339243A (ja) * | 2005-05-31 | 2006-12-14 | Toshiba Corp | 半導体装置 |
JP2007088158A (ja) * | 2005-09-21 | 2007-04-05 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2007335573A (ja) * | 2006-06-14 | 2007-12-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2008172234A (ja) * | 2007-01-12 | 2008-07-24 | Internatl Business Mach Corp <Ibm> | 高性能cmos技術のための低コストの歪みsoi基板 |
JP2010527140A (ja) * | 2007-02-12 | 2010-08-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電界効果トランジスタ(FET)の製造方法、n型およびp型電界効果トランジスタ |
JP2010010473A (ja) * | 2008-06-27 | 2010-01-14 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2010183065A (ja) * | 2009-01-07 | 2010-08-19 | Fujitsu Ltd | 半導体およびその製造方法 |
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