JP4796771B2 - 半導体デバイス - Google Patents
半導体デバイス Download PDFInfo
- Publication number
- JP4796771B2 JP4796771B2 JP2004547063A JP2004547063A JP4796771B2 JP 4796771 B2 JP4796771 B2 JP 4796771B2 JP 2004547063 A JP2004547063 A JP 2004547063A JP 2004547063 A JP2004547063 A JP 2004547063A JP 4796771 B2 JP4796771 B2 JP 4796771B2
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- layer
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- dopant
- gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Description
本出願は、2002年10月22日に出願された米国特許仮出願第60/420227号の利益を主張し、その開示内容全体は、参照により本明細書に組み込まれている。
技術分野
本発明は、一般的には半導体デバイスに関し、特に歪み層を備えている半導体基板上に形成された半導体構造に関する。
半導体層を予めドーピングし、ゲート画定前にドーパント分布のためのアニールを行う。浅いソースおよびドレインは、その後に形成されるので、ゲートのアニールステップの影響を受けない。
手段
一実施態様では、本発明は、構造を形成する方法に関し、この方法は、基板上に、約2nm(約20Å)より薄い厚みを有する空乏領域を備えている層を形成することを含む。そして、層の一部を除去してトランジスタのゲートを画定し、このゲートがチャンネル長さを規定する。複数のドーパントをゲート付近の基板に導入してソースおよびドレインを画定し、導入された複数のドーパントが活性化する温度に基板を加熱する。この温度は、複数のドーパントの少なくとも一部が拡散して高いOFF電流が生じてしまうことを防止するには十分に低くなっている。
Claims (44)
- 半導体デバイスを形成する方法であって、
基板上に設けられた、半導体からなるゲート電極層の第1の部分に、第1のドーパントを導入すること、
前記ゲート電極層の第1の部分内の第1のドーパントを均一に分布させるために、当該ゲート電極層を第1の温度に加熱すること、
前記ゲート電極層の前記第1の部分以外の部分を除去してトランジスタのゲートを画定して、該ゲートがチャンネル長さを画定すること、
前記ゲートに隣接している前記基板に第2のドーパントを導入してソースおよびドレインを画定すること、および
前記第2のドーパントを活性化させるために、前記基板を前記第1の温度よりも低い第2の温度に加熱することによって、前記ゲート電極層が2nm(20オングストローム)より小さな空乏領域を備えていることを含む、方法。 - 前記基板が絶縁体層を含む、請求項1に記載の方法。
- 前記基板が、前記絶縁体層上に設けられた歪み層を含む、請求項2に記載の方法。
- 前記基板が歪み層を含む、請求項1に記載の方法。
- 前記歪み層が引張り歪みを有している、請求項4に記載の方法。
- 前記歪み層が圧縮歪みを有している、請求項4に記載の方法。
- 前記基板が緩和層を含む、請求項1に記載の方法。
- 前記基板がゲルマニウムからなっている、請求項1に記載の方法。
- 前記半導体デバイスのOFF電流が、1マイクロメートルあたり10−6アンペアより小さい、請求項1に記載の方法。
- 前記半導体デバイスのOFF電流が、1マイクロメートルあたり10−9アンペアより小さい、請求項9に記載の方法。
- 前記基板の加熱後、前記ソースが前記ゲート下で広がり、その広がる距離がチャンネル長さの12.5%よりも短い、請求項1に記載の方法。
- 前記基板の加熱後、前記ドレインが前記ゲート下で広がり、その広がる距離がチャンネル長さの12.5%よりも小さい、請求項1または11に記載の方法。
- 前記半導体がシリコンを含む、請求項1に記載の方法。
- 前記半導体がゲルマニウムを含む、請求項1に記載の方法。
- 前記第1のドーパントおよび第2のドーパントが、n型ドーパントからなっている、請求項1に記載の方法。
- 前記第1のドーパントおよび第2のドーパントが、p型ドーパントからなっている、請求項1に記載の方法。
- 半導体デバイスを形成する方法であって、
基板上に設けられた、半導体からなるゲート電極層に、第1のドーパントを導入すること、
前記ゲート電極層内の第1のドーパントを均一に分布させるために、当該ゲート電極層を第1の温度に加熱すること、
前記ゲート電極層の一部を除去して、トランジスタのゲートを画定すること、
第2のドーパントを前記ゲートに隣接する前記基板に導入して、ソースおよびドレインを画定すること、および
前記第2のドーパントを活性化させるために、前記基板を前記第1の温度よりも低い第2の温度に加熱することによって、前記ゲート電極層が2nm(20オングストローム)より小さな空乏領域を備えていることを含む、方法。 - 前記基板が絶縁体層を含む、請求項17に記載の方法。
- 前記基板が、前記絶縁体層上に設けられた歪み層を含む、請求項18に記載の方法。
- 前記基板が歪み層を含む、請求項17に記載の方法。
- 前記歪み層が引張り歪みを有している、請求項20に記載の方法。
- 前記歪み層が圧縮歪みを有している、請求項20に記載の方法。
- 前記基板が緩和層を含む、請求項17に記載の方法。
- 前記基板がゲルマニウムを含む、請求項17に記載の方法。
- 前記第1の温度が1273K(1000℃)よりも高い、請求項17に記載の方法。
- 前記第2の温度が1273K(1000℃)よりも低い、請求項17に記載の方法。
- 前記半導体層がシリコンを含む、請求項17に記載の方法。
- 前記半導体層がゲルマニウムを含む、請求項17に記載の方法。
- 前記第1のドーパントおよび第2のドーパントが、n型ドーパントからなっている、請求項17に記載の方法。
- 前記第1のドーパントおよび第2のドーパントが、p型ドーパントからなっている、請求項17に記載の方法。
- 半導体デバイスを形成する方法であって、
基板上に設けられた、半導体からなるゲート電極層に、第1のドーパントを導入すること、
前記ゲート電極層内の前記第1のドーパントを均一に分布させるために、当該ゲート電極層を第1の時間加熱すること、
前記ゲート電極層の一部を除去して、トランジスタのゲートを画定すること、
第2のドーパントを前記ゲートに隣接する前記基板に導入して、ソースおよびドレインを画定すること、
前記第2のドーパントを活性化させるために、前記基板を前記第1の時間よりも短い第2の時間加熱することによって、前記ゲート電極層が2nm(20オングストローム)より小さな空乏領域を備えていることを含む、方法。 - 前記基板が絶縁体層を含む、請求項31に記載の方法。
- 前記基板が、前記絶縁体層上に設けられた歪み層を含む、請求項32に記載の方法。
- 前記基板が歪み層を含む、請求項31に記載の方法。
- 前記歪み層が引張り歪みを有している、請求項34に記載の方法。
- 前記歪み層が圧縮歪みを有している、請求項34に記載の方法。
- 前記基板が緩和層を含む、請求項31に記載の方法。
- 前記基板が、シリコンおよびゲルマニウムの少なくとも1つを含む、請求項31に記載の方法。
- 前記第1の時間が5秒よりも長い、請求項31に記載の方法。
- 前記第1の時間が30秒より長い、請求項31に記載の方法。
- 前記半導体層がシリコンを含む、請求項31に記載の方法。
- 前記半導体層がゲルマニウムを含む、請求項31に記載の方法。
- 前記第1のドーパントおよび前記第2のドーパントがn型ドーパントからなっている、請求項31に記載の方法。
- 前記第1のドーパントおよび前記第2の複数のドーパントがp型ドーパントからなっている、請求項31に記載の方法。
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PCT/US2003/033561 WO2004038778A1 (en) | 2002-10-22 | 2003-10-22 | Gate material for semiconductor device fabrication |
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2003
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- 2003-10-22 JP JP2004547063A patent/JP4796771B2/ja not_active Expired - Lifetime
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- 2003-10-22 EP EP03809619A patent/EP1561238A1/en not_active Ceased
- 2003-10-22 WO PCT/US2003/033561 patent/WO2004038778A1/en active Application Filing
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2005
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Also Published As
Publication number | Publication date |
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US20060258075A1 (en) | 2006-11-16 |
WO2004038778A1 (en) | 2004-05-06 |
US20040137685A1 (en) | 2004-07-15 |
AU2003301603A1 (en) | 2004-05-13 |
US7326599B2 (en) | 2008-02-05 |
US6991972B2 (en) | 2006-01-31 |
JP2006505116A (ja) | 2006-02-09 |
US20060024869A1 (en) | 2006-02-02 |
US7074655B2 (en) | 2006-07-11 |
EP1561238A1 (en) | 2005-08-10 |
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