JP2006147650A - 電子素子の実装方法、電子装置の製造方法、回路基板、電子機器 - Google Patents
電子素子の実装方法、電子装置の製造方法、回路基板、電子機器 Download PDFInfo
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- JP2006147650A JP2006147650A JP2004331965A JP2004331965A JP2006147650A JP 2006147650 A JP2006147650 A JP 2006147650A JP 2004331965 A JP2004331965 A JP 2004331965A JP 2004331965 A JP2004331965 A JP 2004331965A JP 2006147650 A JP2006147650 A JP 2006147650A
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Abstract
【解決手段】 配線基板上に電子素子(半導体チップ)を能動面を表側にして接合する(ダイボンド工程)。続いて、電子素子の周囲に、配線基板の表面から電子素子の能動面に繋がる斜面を形成し(スロープ形成工程)、この斜面の表面に液滴吐出法により能動面上の電極端子と配線基板上の配線パターンとを接続する金属配線を形成する(金属配線形成工程)。本発明においては、金属配線を形成する前に、当該金属配線が形成される電子素子の能動面にエポキシ樹脂やウレタン樹脂等からなる有機絶縁膜を形成し(絶縁インク処理工程)、密着性を向上させる。
【選択図】 図2
Description
本発明はこのような事情に鑑みてなされたものであり、電子素子を配線基板に実装する際の機械的ストレスを低減し、接続信頼性の高い実装構造を低コストで実現することのできる電子素子の実装方法を提供することを目的とする。
このような材料を用いることで、より密着性を向上させることができる。例えば、SiO2又はSiNを下地として金属配線を形成した場合の密着力は1000g/mm2であるのに対して、エポキシ樹脂又はウレタン樹脂を下地として同様に金属配線を形成した場合の密着力は5000g/mm2であった。また、テープ剥離試験においても、前者の場合は完全に剥離したのに対して、後者の場合は剥離せずに残った。
この方法によれば、必要な部分にのみ選択的に有機絶縁膜を形成することができる。
前述したように、実際の電子素子の表面は平坦ではなく、種々の凹凸が形成されている。このような凹凸が存在すると、液滴はその凹凸の段差面に沿って濡れ広がり、隣接する配線同士がショートしたりする場合がある。本発明の方法では、このような段差面での濡れ広がりを防止するために、有機絶縁膜の描画を2回に分けて行なっている。本方法では、まず1回目に段差部を避けて液滴を吐出し、これを乾燥して段差部の前後に第1の有機絶縁膜を形成する。そして2回目に、それらを繋ぐように段差部を跨いで前後の第1の有機絶縁膜に重なるように液滴を吐出する。液滴の上に液滴を重ね描きする場合、上層側の液滴は着弾位置に定着し易いので、2回目の液滴は両側を固定された状態となり、段差面に沿って大きく濡れ広がることがない。よって、段差部の影響を殆ど受けずに所望のパターンを形成することができる。
これらの方法によれば、有機絶縁膜や接続配線を形成する際に液滴の定着性を良好なものとすることができる。
この方法によれば、接続信頼性の高い電子装置を低コストで提供することができる。
この構成によれば、接続信頼性の高い回路基板及び電子機器を低コストで提供することができる。
以下、図面を参照しながら、本発明の実施の形態について説明する。以下の全ての図面においては、図面を見やすくするため、各構成要素の膜厚や寸法の比率などは適宜異ならせてある。
図1は本発明の電子機器の一例である液晶表示装置を示す分解斜視図である。
図1の液晶表示装置100は、液晶パネル13と駆動用の回路基板10とを有する。また、必要に応じて、バックライト等といった照明装置、その他の付帯構造が液晶パネル13に付設される。液晶パネル13は、シール材133によって周縁が互いに接着された一対の基板131および132を有し、それらの基板間に形成された間隙、いわゆるセルギャップに、例えばSTN(Super Twisted Nematic)型の液晶が封入されて構成されている。基板131および132は例えばガラスや合成樹脂等の透光性材料によって構成される。基板131および132の外側には偏光板140が貼着され、少なくとも一方の基板131,132と偏光板140との間に位相差板(図示せず)が挿入されている。そして、一方の基板131の内側表面には表示用電極131aが形成され、他方の基板132の内側表面には表示用電極132aが形成されている。これらの表示用電極131a,132aはストライプ状または文字、数字、その他の適宜のパターン状に形成される。また、これらの表示用電極131a,132aは、例えばITO(Indium Tin Oxide:インジウムスズ酸化物)等といった透光性導電材料によって形成されている。
次に、本発明の電子装置の一例である液晶駆動用IC12(以下、単にICという)について説明する。本実施形態において、IC12は、ガラスエポキシ2層基板からなる配線基板に電子素子である半導体チップ(ベアチップ)を実装し、裏面側にBGAを配してパッケージング化したものである。
以下、その製造方法について説明する。
本実施形態のIC12の製造方法は、半導体チップを配線基板に実装する方法としてフェースアップ実装方式を採用し、配線接続の方法として、従来のワイヤボンディングの代わりに、液滴吐出方式によって形成した金属配線(接続配線)を用いて接続する方法を採用している。本実施形態のIC12の製造方法は、(1)ダイボンド工程、(2)絶縁インク処理工程、(3)スロープ形成工程、(4)金属配線形成工程、(5)パッケージ化工程、の5つの工程を備えている。なお、製造方法はこれに限られるものではなく、必要に応じてその他の工程が除かれる場合、また追加される場合もある。
まず、専用の治具を用いて半導体チップ(ベアチップ)を配線基板に接合する。
図3は、ダイボンド装置の構成を示す図であり、図3(a)は概略構成を示す斜視図、図3(b)は実装装置の要部を示す側断面図である。
テーブル部51は、ダイボンド装置50本体の下方に設けられたものである。そして、移動テーブル部53がXステージ53x及びYステージ53yを備えることにより、基板ホルダ54をXY方向に自由に移動可能となると共に、任意位置に固定することが可能となっている。更に、テーブル部51は半導体素子搭載部55を備え、当該半導体素子搭載部55には、実装前の複数の半導体チップ3が搭載されている。更に、基板ホルダ54には、上記の配線基板2が載置されるようになっている。配線基板2としては、例えばガラスエポキシ2層基板が用いられる。配線基板2には、半導体チップ3を実装するための矩形の実装領域Eが設けられており、この実装領域Eの周囲には、半導体チップ3の電極端子と接続するための多数の配線パターン2aが形成されている。半導体チップ3には能動面側に電子回路(集積回路)が形成されており、この電子回路が形成された能動面上には、その電子回路の外部電極となる電極端子が形成されている。本実施形態では、この能動面を表側にして半導体チップ3を実装する。
図4は、接合過程を示す断面図である。
まず、図4(a)に示すように、加熱加圧工具59が半導体チップ3を吸着保持し、基板ホルダ54が配線基板2を吸着固定する。具体的には、上下移動機構57及び移動テーブル部53が駆動することにより、加熱加圧工具59が半導体素子搭載部55に搭載されている半導体チップ3を吸着保持した後に、当該半導体チップ3を保持しつつ、配線基板2に対向配置させる。また、基板ホルダ54においては、吸着孔54a,54bが吸着動作を行う。
以上の工程が終了したら、加熱及び加圧を停止し、上下移動機構57を伸縮させて加熱加圧工具59を配線基板2から離間させる。これにより、半導体チップ3が配線基板2の実装領域に能動面を表側にして接合される。
次に、図6に示すように、半導体チップ3の能動面3aに絶縁インク(絶縁性材料を含む液滴)を吐出し、該能動面3a上に有機絶縁膜7を形成する。この有機絶縁膜7は、後述の金属配線8を形成するための準備として行なわれるものである。
有機絶縁膜7としてはエポキシ樹脂やウレタン樹脂を用いることが望ましい。実際に、これらの材料を用いることで、非常に密着性のよい接続配線8を形成できるようになる。例えば、SiO2又はSiNを下地として金属配線8を形成した場合の密着力は1000g/mm2であるのに対して、エポキシ樹脂又はウレタン樹脂を下地として同様に金属配線8を形成した場合の密着力は5000g/mm2であった。また、テープ剥離試験においても、前者の場合は完全に剥離したのに対して、後者の場合は剥離せずに残った。
図8は、その液滴吐出装置の一例であるインクジェット装置の斜視図である。図8において、X方向はベース212の左右方向であり、Y方向は前後方向であり、Z方向は上下方向である。液滴吐出装置210は、液滴吐出ヘッド(以下、単にヘッドと呼ぶ)220と、配線基板2を載置するテーブル246とを主として構成されている。なお、液滴吐出装置210の動作は、制御装置223により制御されるようになっている。
本実施形態では、まず前処理として、半導体チップ3をUV処理装置(波長λ=254nm)で10分間処理する。この工程によって、半導体チップ3の能動面3aが親液化される。能動面を親液化する処理としては、UV処理以外のドライ或いはウェット処理を行なうことも可能である。これらの処理においては、能動面上における液滴の接触角が90°以下、より好ましくは20°以下となるようにすることが望ましい。なお、親液化処理しなくても前記接触角になっている場合には、このような処理は不要である。
本実施形態では、液滴の吐出を2回の工程に分けて行なう。まず1回目の工程では、電極端子5や段差部であるガードリング9を避けて、電極端子5から能動面3aの端部方向に塗り残しなく液滴61を滴下する。液滴61の滴下パターンは、液滴同士の間に隙間ができないように、隣接する着弾液滴と1/3程度重なるピッチとすることが望ましい。滴下位置の位置決めは、能動面3a上のアライメントマーク(図示略)を利用して行なう。このアライメントマークは液滴が配置されない位置に設置されている。1回目の工程が終了したら、図7(b)に示すように、液滴61を乾燥して第1の乾燥膜(第1の有機絶縁膜)61aを形成する。そして、2回目の工程として、段差部であるガードリング9に対して液滴62を滴下し、これを乾燥して、前後の乾燥膜61aに跨る第2の乾燥膜(第2の有機絶縁膜)を形成する。
なお、図6では、有機絶縁膜7を能動面3aの外周部にのみ形成しているが、本発明はこれに限定されない。有機絶縁膜7を電極端子5を除く能動面全体に形成することも可能である。
次に、半導体チップ3の周囲に樹脂材料を塗布し、配線基板2の表面から半導体チップ3の能動面3aに繋がるスロープ(斜面)6Aを形成する(図11参照)。このスロープ6Aは、半導体チップ3の厚み(接着層を含む)による段差を緩和し、その後の金属配線8の形成を容易にするために用いられるものである。
なお、樹脂材料としては、例えばエポキシ系の熱硬化性樹脂を用いることができる。この樹脂材料は、プリベーク処理(90℃、30分)およびポストベーク処理(150℃、2時間)によって硬化させることができる。一般に樹脂材料は熱硬化工程で体積収縮を起こす。このため、本工程においては、能動面3aから配線基板表面になだらかなスロープを形成するために2〜3回の樹脂塗布を行なうものとする。複数回塗布する場合には、プリベーク処理を塗布時に行ない、ポストベークは一括で行なうものとする。
なお、本工程において、予備吐出はディスペンサノズルの吐出遅れの問題を解決するために行なうものである。このため、吐出量はそれ程多くする必要はない。むしろ吐出量を必要最小限にする(少なくとも半導体チップ3の縁辺に沿って行なわれる本吐出の吐出量よりも少なく設定する)ことで、配線パターン2aの被覆の問題や吐出の無駄を回避することが望ましい。
なお、本工程においては、経路D1〜D4の塗布工程はどれを先に行なってもよい。また、順番も問わない。本実施形態では、この順番を例えばD1,D3,D2,D4の順に行なっている。
本実施形態において、樹脂層6は、半導体チップ3の縁辺に沿って配置された第1の樹脂層6aと、この第1の樹脂層6aから突出した第2の樹脂層6bとを有している。第1の樹脂層6aは、本吐出(第2の経路R2における吐出)によって形成されたものであり、その形状は、半導体チップ3の縁辺に沿う略矩形枠状の形状となっている。第2の樹脂層6bは、予備吐出(第1の経路R1及び第3の経路R3における吐出)によって形成されたものであり、その形状は、第1の樹脂層6aの角部から、当該角部を含む2つの縁辺のいずれに対しても鈍角となる方向に突出する形状となっている。第2の樹脂層6bは第1の樹脂層の全ての角部に設けられており、これら第2の樹脂層6bが半導体チップ3を中心として4方に広がるように配置されている。本実施形態の樹脂層6は金属配線8を形成するための斜面として形成するものであるが、同時に、半導体チップ3を配線基板2上に固定する固定層としての役割も有している。樹脂層6を一筆書き式に形成した場合には、形成される樹脂層は第1の樹脂層6aのみとなるが、本実施形態では予備吐出によって第2の樹脂層6bを形成しているので、その分、チップの固定力は強くなる。また、第1の樹脂層6aと第2の樹脂層6bは半導体チップ3を中心として略対称な配置となるので、半導体チップ3に対する樹脂層6の影響を均一化することができる。
次に、図12に示すように、スロープ6Aと有機絶縁膜7の表面に液滴吐出法により金属配線8を形成する。この金属配線8は、能動面3a上に設けられた電極端子5と前記配線基板2上に設けられた配線パターン2aとを接続する接続配線である。
図13(a)は電極端子5の近傍を模式的に示す平面図である。この図において、符号70は膜パターンを形成しようとする線状の膜形成領域であり、符号Bは半導体チップ3と樹脂層6との境界部を示している。境界部Bの前後では、液滴を吐出する吐出面の表面性が異なっている。また、境界部Bと電極端子5との間に段差部であるガードリング9が配置されている。本工程においては、これらガードリング9及び境界部Bを介して連続した線状の膜パターンを形成することになる。
また本実施形態では、バルジを生じないように、1回目及び2回目の工程において液滴を互いに接触させないように吐出した。しかし、バルジは隣接する膜パターン(金属配線)が接触しない範囲で許容されるため、これらの工程においては、液滴を複数滴ずつ連続して(繋げて)滴下することも可能である。この場合、連続して滴下される液滴の数は、当該液滴を繋げて配置したときに、これらによって形成される液状膜の幅が対象となる膜パターンのピッチ(本工程の場合は線状パターンである金属配線8の配列ピッチ)以下となるような数に設定する必要がある。このように複数の液滴を繋げてパターンを形成した場合には、ある程度幅広の線状パターンを形成することができる。
金属配線8が形成されたら、配線基板2の半導体チップ3が実装された面を必要に応じてモールディングする。そして、配線基板2の裏面側にはんだボールを搭載し、リフロー工程、洗浄工程、シート貼り付け工程を経た後、基板切断を行なって個片化する。
以上により、IC12の製造が完了する。
図22は、ガードリング付近の金属配線の様子を示す図である。図22(a)は下地膜として有機絶縁膜7を形成した場合における金属配線の様子を示す図(本実施形態の方法を用いた例)であり、図22(b)は有機絶縁膜7を形成せずに、SiO2等のパッシベーション膜の表面に直接配線描画を行なった場合における金属配線の様子を示す図である。図22(b)では、ガードリングの段差面を介して液滴が広がり、金属配線同士が図の円で囲った部分においてショートしている。これに対して、図22(a)では、液滴の広がりが図の円で囲った部分の範囲内に留まっており、金属配線が均一な幅で形成されていることがわかる。
例えば本実施形態では、本発明の電子素子として半導体チップ3を例に挙げたが、電子素子はこれに限らず、コンデンサや抵抗などの半導体素子以外の素子を用いることもできる。また、先に示した製造工程(1)〜(5)は、工程に矛盾を生じない範囲で部分的に順番を換えてもよい。例えば(2)の絶縁インク処理工程と(3)のスロープ形成工程は入れ替えが可能である。また本実施形態では、配線パターン2aが半導体チップ3の全ての縁辺に対して配置されているものとしたが、本発明は必ずしもこれに限るものではない。例えば2辺或いは3辺のみとすることもできる。
また本実施形態では、ベアチップをIC12にパッケージ化してからフィルム基板11に実装する構成としたが、ベアチップをパッケージ化せずに、直接フィルム基板11にマウントする構成としてもよい。この場合、フィルム基板11が本発明の配線基板となる。電子素子であるベアチップの(1)ダイボンド工程、(2)絶縁インク処理工程、(3)スロープ形成工程、(4)金属配線形成工程、(5)パッケージ化工程等については前述の工程と同様のものを採用することができる。
次に、本発明の第2の実施形態について説明する。
本実施形態において第1の実施形態と異なる点は、半導体チップ3の接合工程のみである。よって、ここでは当該工程についてのみ説明する。なお、本実施形態において第1の実施形態と同様の部材又は部位については同じ符号を付し、詳細な説明は省略する。
第1の実施形態では、接着層の厚みを薄くするために、接着剤4を小径化して接合部内に分散配置した。これに対して、本実施形態では接着剤4は小径化せずに塊として配置する。その代わりに、配線基板2に貫通孔2Hを形成し、この貫通孔2H内に余分な接着剤を排出するようにしている。接着剤4は、加熱加圧工具59で加圧する際に、貫通孔2Hを介して配線基板2の裏面側に排出される。このとき、排出をスムーズに行なうために、配線基板2の裏面側に配置した吸引手段(例えば吸着孔54a,54b)を用いて吸引してもよい。この方法によれば、仮に接着剤4が多く配置されたとしても、余分な接着剤4は貫通孔2Hを介して配線基板2の裏面側に排出されるため、接着層の厚みに寄与しない。このため、従来よりも薄い接着層を形成することができる。
本形態では、配線基板2に凹部2Dを形成し、この凹部2D内に余分な接着剤4を排出するようにしている。すなわち、本形態では半導体チップ3の接着が、余分な接着剤4を凹部2Dに逃がしながら行なわれるようになっている。このため、仮に接着剤4が多く配置されたとしても、余分な接着剤4は凹部2D内に収容されるため、接着層の厚みに寄与しない。
次に、本発明の第3の実施形態について説明する。
本実施形態において第1の実施形態と異なる点は、スロープの形成工程のみである。よって、ここでは当該工程についてのみ説明する。なお、本実施形態において第1の実施形態と同様の部材又は部位については同じ符号を付し、詳細な説明は省略する。
第1の実施形態では、ディスペンサの吐出開始位置SPと吐出終了位置EPとを半導体チップ3の角部から当該縁辺に対して斜めにずれた位置に配置し、予備吐出に係る経路R1とR3を本吐出に係る経路R2に対して屈曲した経路とした。これに対して、本実施形態では、これらの経路R1〜R3を一直線上に配置している。本方法は、配線パターン2aが半導体チップ3の縁辺ぎりぎりまで配置されていない場合に利用可能な方法である。この方法においては、第1の実施形態の場合と同様に、各縁辺におけるディスペンサの移動方向を、それぞれ半導体チップ3を中心として時計回りの方向又は反時計回りの方向に揃うように設定することが望ましい。これにより、樹脂量の多い部分や少ない部分が偏在することを防ぐことができる。
本形態では、ディスペンサの吐出開始位置SPが半導体チップ3の角部に近接して配置されている。この場合、吐出開始位置SP付近では、樹脂材料の吐出量が少なくなる傾向にある。このため、本形態では、各縁辺に対する樹脂材料の塗布工程において、これら全ての縁辺におけるディスペンサの移動方向を、それぞれ半導体チップ3を中心として時計回りの方向又は反時計回りの方向に揃うように設定している。本方法によれば、半導体チップ3の各角部に、一方の縁辺における吐出開始位置SPと、他方の縁辺における吐出終了位置EPの双方が配置されるため、一方の縁辺に対する塗布工程において吐出不足となった部分を、他方の縁辺に対する塗布工程において吐出過多となった部分で補うことができる。よって、各縁辺に対して均一な塗布が可能になる。
また、本形態においては、ディスペンサの吐出開始位置SP又は吐出終了位置EPのうち、半導体チップ3から離れた位置に設定されたものの位置が、半導体チップ3の角部から、当該角部を含む2つの縁辺のいずれに対しても鈍角となる方向に配置されていることが望ましい。これにより、配線群2Aとの干渉を避けることができる。
次に、本実施形態の電子装置又は回路基板を備えた電子機器につき、図21を用いて説明する。図21は、携帯電話の斜視図である。図21において符号1000は携帯電話を示し、符号1001は表示部を示している。この携帯電話1000の表示部1001には、本実施形態の電子装置又は回路基板を備えた電気光学装置(例えば前述の液晶表示装置)が採用されている。したがって、電気的接続の信頼性に優れた小型の携帯電話1000を提供することができる。
本発明は、上記携帯電話に限らず、電子ブック、パーソナルコンピュータ、ディジタルスチルカメラ、液晶テレビ、ビューファインダ型あるいはモニタ直視型のビデオテープレコーダ、カーナビゲーション装置、ページャ、電子手帳、電卓、ワードプロセッサ、ワークステーション、テレビ電話、POS端末、タッチパネル等の電子機器の画像表示手段として好適に用いることができ、いずれの場合でも、電気的接続の信頼性に優れた小型の電子機器を提供することができる。
Claims (9)
- 配線基板に電子素子を実装する電子素子の実装方法であって、
前記配線基板に前記電子素子を配置する工程と、
前記能動面上に有機絶縁膜を形成する工程と、
前記電子素子の周囲に、前記配線基板の表面から前記電子素子の能動面に繋がる斜面を形成する工程と、
前記斜面と前記有機絶縁膜の表面に、液滴吐出法により、前記電子素子に設けられた電極端子と前記配線基板上に設けられた配線パターンとを接続する接続配線を形成する工程とを備えたことを特徴とする、電子素子の実装方法。 - 前記有機絶縁膜が、エポキシ樹脂又はウレタン樹脂からなることを特徴とする、請求項1記載の電子素子の実装方法。
- 前記有機絶縁膜が、液滴吐出法により形成されることを特徴とする、請求項1又は2記載の電子素子の実装方法。
- 前記能動面に段差部が形成されており、
前記有機絶縁膜の形成工程が、液滴吐出法により前記段差部の前後に第1の有機絶縁膜を形成する工程と、液滴吐出法により前記段差部の前後の前記第1の有機絶縁膜に跨る第2の有機絶縁膜を形成する工程とを含むことを特徴とする、請求項3記載の電子素子の実装方法。 - 前記有機絶縁膜を形成する前に、前記能動面を親液化する工程を含むことを特徴とする、請求項3又は4記載の電子素子の実装方法。
- 前記接続配線を形成する前に、前記有機絶縁膜の表面を親液化する工程を含むことを特徴とする、請求項1〜5のいずれかの項に記載の電子素子の実装方法。
- 配線基板上に電子素子を実装してなる電子装置の製造方法であって、
前記電子素子の実装工程が、請求項1〜6のいずれかの項に記載の電子素子の実装方法を用いて行なわれることを特徴とする、電子装置の製造方法。 - 請求項7記載の方法により製造されてなる電子装置を備えたことを特徴とする、回路基板。
- 請求項7記載の方法により製造されてなる電子装置又は請求項8記載の回路基板を備えたことを特徴とする、電子機器。
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KR1020050107844A KR100676156B1 (ko) | 2004-11-16 | 2005-11-11 | 전자 소자의 실장 방법, 전자 장치의 제조 방법, 회로 기판및 전자 기기 |
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US20060103788A1 (en) | 2006-05-18 |
TWI282596B (en) | 2007-06-11 |
KR100676156B1 (ko) | 2007-02-01 |
CN1790653A (zh) | 2006-06-21 |
JP3992038B2 (ja) | 2007-10-17 |
TW200634956A (en) | 2006-10-01 |
CN100397603C (zh) | 2008-06-25 |
KR20060055342A (ko) | 2006-05-23 |
US7454831B2 (en) | 2008-11-25 |
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