JP2006080343A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2006080343A JP2006080343A JP2004263670A JP2004263670A JP2006080343A JP 2006080343 A JP2006080343 A JP 2006080343A JP 2004263670 A JP2004263670 A JP 2004263670A JP 2004263670 A JP2004263670 A JP 2004263670A JP 2006080343 A JP2006080343 A JP 2006080343A
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】 LDMOSFETのゲート電極30およびn+型ソース領域53上にサリサイド工程により金属シリサイド膜64を形成し、n-型オフセットドレイン領域33、n型オフセットドレイン領域51およびn+型ドレイン領域52上にはこの金属シリサイド膜を形成しない。ゲート電極30のドレイン側の側壁上には、絶縁膜を介して、シリコン膜からなるサイドウォールスペーサが形成され、このサイドウォールスペーサによりフィールドプレート電極44が形成される。フィールドプレート電極44はゲート電極30上に延在しておらず、サリサイド工程ではゲート電極30の上面の全面に金属シリサイド膜64が形成される。
【選択図】 図19
Description
ηadd=ηd(1−1/GP)
と表される。
ηd=kγ(1−Ron/(Vdd×Id))
で表され、パワーゲイン(power gain)GPは、第3式
GP=(fT/f)2×((4gd(Ri+Rs+Rg+πfTLs)+4πfTCgd(Ri+Rs+2Rg+2πfTLs))-1
で表される。
2 半導体チップ
2a電極
2b 裏面電極
3 配線基板
3a 上面
3b 下面
4 受動部品
5 封止樹脂
8 ボンディングワイヤ
11 絶縁体層
12a 基板側端子
12b 外部接続端子
12c 基準電位供給用端子
13 ビアホール
13a ビアホール
14 窪み
14a 導体層
15 半田
17 半田
21 基板
22 エピタキシャル層
23 溝
24 p型打抜き層
26 p型ウエル
28 ゲート絶縁膜
28a 絶縁膜
29 n型多結晶シリコン膜
30 ゲート電極
30a 引き出し部
31 側壁絶縁膜
33 n-型オフセットドレイン領域
34 n型ソース領域
35 p型ハロー領域
41 絶縁膜
42 シリコン膜
43 サイドウォールスペーサ
44 フィールドプレート電極
44a 引き出し部
45 フォトレジストパターン
51 n型オフセットドレイン領域
52 n+型ドレイン領域
53 n+型ソース領域
55 p+型半導体領域
61 絶縁膜
62 フォトレジストパターン
62a フォトレジストパターン
63 金属膜
64 金属シリサイド膜
71 絶縁膜
72 コンタクトホール
72a コンタクトホール
72b コンタクトホール
72c コンタクトホール
72d コンタクトホール
72e コンタクトホール
73 プラグ
73a プラグ
73b プラグ
73c プラグ
74 配線
74a ドレイン電極
74b ソース電極
75 絶縁膜
76 スルーホール
77 プラグ
78 配線
79 表面保護膜
81 裏面電極
102A,102B 電力増幅回路
102A1,102A2,102A3,102B1,102B2,102B3 増幅段
102AM1,102AM2,102BM1,102BM2 整合回路
103 周辺回路
103A 制御回路
103A1 電源制御回路
103A2 バイアス電圧生成回路
103B バイアス回路
104a,104b 入力端子
105A,105B 整合回路
106a,106b 出力端子
107A,107B 整合回路
108A,108B ローパスフィルタ
110 高周波モジュール
111 HPA部
112 高周波IC部
113 ベースバンドLSI部
115 送受信用アンテナ
116 送受信切り替え用スイッチ回路
117 パワーアンプモジュール
118 高周波フィルタ
119 LNA
119A 増幅器
119B 復調回路
120 PGA
121 デジタル制御水晶発振器
122 RFVCO
123 出力制御部
124 VGA
125 変調回路
126 レギュレータ
131 LDMOSFET形成領域
132 ドレインパッド
133 ゲートパッド
134 領域
135 単位セル
135a 単位LDMOSFET
142 酸化シリコン膜
143 サイドウォールスペーサ
151 マザーボード
152 チップ部品
153 接合材153
241 絶縁膜
242 シリコン膜
243 フォトレジストパターン
244 フィールドプレート電極
Claims (20)
- シリコンからなる半導体基板主面に形成されたソース領域、ドレイン領域およびゲート電極を有するLDMOSFETを含む半導体装置であって、
第1導電型の前記半導体基板と、
前記半導体基板上にゲート絶縁膜を介して形成され、シリコンからなる前記ゲート電極と、
前記半導体基板の主面に形成された第2導電型の前記ソース領域と、
前記半導体基板の主面に形成された第2導電型の前記ドレイン領域と、
を有し、
前記ゲート電極上および前記ソース領域上に金属シリサイド膜が形成され、前記ドレイン領域上に金属シリサイド膜が形成されていないことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート電極の前記ドレイン領域側の側面上に絶縁膜を介して形成されたサイドウォールスペーサ状のフィールドプレート電極を更に有することを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記フィールドプレート電極がシリコン膜からなることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記フィールドプレート電極は導電体膜をエッチバックすることにより形成されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記ゲート電極の上面に前記金属シリサイド膜が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート電極上に形成された前記金属シリサイド膜と前記ソース領域上に形成された前記金属シリサイド膜とが、同種の金属シリサイドからなることを特徴とする半導体装置。 - 半導体基板主面に形成されたソース領域、ドレイン領域およびゲート電極を有するLDMOSFETを含む半導体装置であって、
第1導電型の前記半導体基板と、
前記半導体基板上にゲート絶縁膜を介して形成された前記ゲート電極と、
前記半導体基板の主面に形成された第2導電型の前記ソース領域と、
前記半導体基板の主面に形成された第2導電型の前記ドレイン領域と、
前記ゲート電極の前記ドレイン領域側の側面上に絶縁膜を介して形成されたサイドウォールスペーサ状のフィールドプレート電極と、
を有することを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記ゲート電極上面に前記フィールドプレート電極が延在していないことを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記フィールドプレート電極がシリコン膜からなることを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記フィールドプレート電極は導電体膜をエッチバックすることにより形成されていることを特徴とする半導体装置。 - 配線基板と、前記配線基板上に搭載された半導体チップとを有する半導体装置であって、
前記半導体チップは、第1導電型の半導体基板にゲート絶縁膜を介して形成されたゲート電極と、前記半導体基板の主面に形成された第2導電型の前記ソース領域と、前記半導体基板の主面に形成された第2導電型の前記ドレイン領域とを有するLDMOSFETにより形成された増幅回路を含み、
前記ゲート電極上および前記ソース領域上に金属シリサイド膜が形成され、前記ドレイン領域上に金属シリサイド膜が形成されていないことを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
前記半導体装置は、高周波電力増幅モジュールであることを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
前記ゲート電極の前記ドレイン領域側の側面上に絶縁膜を介してサイドウォールスペーサ状のフィールドプレート電極が形成されていることを特徴とする半導体装置。 - 半導体基板主面に形成されたソース領域、ドレイン領域およびゲート電極を有するLDMOSFETを含む半導体装置の製造方法であって、
(a)第1導電型の前記半導体基板を準備する工程、
(b)前記半導体基板の主面上にゲート絶縁膜を介して前記ゲート電極を形成する工程、
(c)前記半導体基板の主面上に前記ゲート電極を覆うように第1絶縁膜を形成する工程、
(d)前記第1絶縁膜上に第1導電体膜を形成する工程、
(e)前記第1導電体膜を異方性エッチングして、前記ゲート電極の前記ドレイン領域側の側面に前記第1導電体膜からなるサイドウォールスペーサ状のフィールドプレート電極を形成する工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記第1導電体膜はシリコン膜からなることを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記(e)工程では、
前記ゲート電極の前記ソース領域側の側面に前記第1導電体膜からなるサイドウォールスペーサ状の導電体部が形成され、
前記(e)工程後に、更に、
(f)前記ゲート電極の前記ソース領域側の側面の前記導電体部を除去し、前記ゲート電極の前記ドレイン領域側の側面の前記フィールドプレート電極を残す工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記(a)工程では、シリコンからなる前記半導体基板が準備され、
前記(b)工程では、シリコンからなる前記ゲート電極が形成され、
前記(f)工程後に、更に、
(g)前記半導体基板の主面上に、前記ゲート電極および前記フィールドプレート電極を覆うように、第2絶縁膜を形成する工程、
(h)前記第2絶縁膜上の前記ドレイン領域上にエッチングマスク層を形成する工程、
(i)前記エッチングマスク層をエッチングマスクとしたエッチングにより、前記ゲート電極上および前記ソース領域上の前記第2絶縁膜を除去し、前記ドレイン領域上に前記第2絶縁膜を残す工程、
(j)前記ゲート電極上および前記ソース領域上に金属シリサイド膜を形成する工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記エッチングマスク層はフォトレジスト層からなることを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記(h)工程では、
前記エッチングマスク層の端部が前記フィールドプレート電極上に位置するように、前記エッチングマスク層が形成されることを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記(j)工程は、
(j1)前記ゲート電極上および前記ソース領域上を含む前記半導体基板上に金属膜を形成する工程、
(j2)熱処理を行い、前記金属膜と前記ゲート電極の上部および前記ソース領域の上部とを反応させて前記金属シリサイド膜を形成する工程、
(j3)未反応の前記金属膜を除去する工程、
を有することを特徴とする半導体装置の製造方法。
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JP2012256885A (ja) * | 2011-06-08 | 2012-12-27 | Great Wall Semiconductor Corp | 相互接続構造の珪化物層およびロープロファイルバンプを有するパワーmosfetを形成する半導体デバイスおよび方法 |
US9006099B2 (en) | 2011-06-08 | 2015-04-14 | Great Wall Semiconductor Corporation | Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump |
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US20060057793A1 (en) | 2006-03-16 |
US7510941B2 (en) | 2009-03-31 |
US8129784B2 (en) | 2012-03-06 |
JP4907070B2 (ja) | 2012-03-28 |
US20090224318A1 (en) | 2009-09-10 |
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