JP2006019698A - 半導体素子の製造方法及び半導体素子 - Google Patents
半導体素子の製造方法及び半導体素子 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 59
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
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- 238000002425 crystallisation Methods 0.000 claims abstract description 31
- 230000008025 crystallization Effects 0.000 claims abstract description 25
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 230000003213 activating effect Effects 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 78
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- 239000004973 liquid crystal related substance Substances 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 12
- 229910004205 SiNX Inorganic materials 0.000 description 9
- 239000011521 glass Substances 0.000 description 9
- 238000004151 rapid thermal annealing Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 230000002411 adverse Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000005224 laser annealing Methods 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 239000000356 contaminant Substances 0.000 description 3
- 238000004880 explosion Methods 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001237 Raman spectrum Methods 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
【解決手段】 基板上に非晶質シリコンを含むシリコンフィルムをPECVD法又はLPCVD法によって蒸着する段階,シリコンフィルムをH2O雰囲気,一定温度下で熱処理して多結晶シリコン膜を形成する段階,多結晶シリコン膜上部にゲート絶縁膜を形成する段階,多結晶シリコン膜に不純物領域を形成してソース/ドレイン領域を定義する段階,及び不純物領域を活性化する段階を含む。
【選択図】図1E
Description
まず,図1に基づいて,第1の実施の形態にかかる半導体素子の製造方法について説明する。なお,図1A〜図1Eは,第1の実施の形態にかかる半導体素子の製造方法を順序的に示した断面図である。
次に,図2A〜図2Eに基づいて,第2の実施の形態にかかる半導体素子の製造方法について説明する。なお,図2A〜図2Eは,第2実施形態にかかる半導体素子の製造方法を順序的に示した断面図である。
次に,図3A〜図3Dに基づいて,第3の実施の形態にかかる半導体素子の製造方法について説明する。なお,図3A〜図3Dは,第3実施形態にかかる半導体素子の製造方法を順序的に示した断面図である。
12 シリコンフィルム
12a 半導体層
14 ゲート絶縁膜
16 ゲート電極
100a ソース/ドレイン領域
100bソース/ドレイン領域
100c アクティブチャネル領域
Claims (25)
- 基板上に非晶質シリコンを含むシリコンフィルムをPECVD法又はLPCVD法によって蒸着する段階と;
前記シリコンフィルムをH2O雰囲気,一定温度下で熱処理して多結晶シリコン膜を形成する段階と;
前記多結晶シリコン膜上部にゲート絶縁膜を形成する段階と;
前記多結晶シリコン膜に不純物領域を形成してソース/ドレイン領域を定義する段階;及び
前記不純物領域を活性化する段階,を含む,
ことを特徴とする半導体素子の製造方法。 - 前記一定温度は,550〜750℃の温度範囲にある,ことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記一定温度は,600〜710℃の温度範囲にある,ことを特徴とする請求項2に記載の半導体素子の製造方法。
- 前記H2Oの圧力は,10,000Pa〜2MPaの圧力範囲にある,ことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記シリコンフィルムの厚さは,2,000オングストローム以下である,ことを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記シリコンフィルムの厚さは,300〜1,000オングストロームの範囲にある,ことを特徴とする請求項5に記載の半導体素子の製造方法。
- 前記不純物領域を活性化する段階は,レーザ熱を照射して前記多結晶シリコン膜のうち結晶化されない非晶質シリコンを結晶化すると同時に前記不純物領域が活性化する段階である,
ことを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記PECVDは,330℃〜430℃の温度範囲で,1〜1.5Torrの圧力範囲で,SiH4+Ar及び/又はH2を用いて実行され,かつ
前記LPCVDは,400〜500℃の温度範囲で,0.2〜0.4Torrの圧力範囲で,Si2H6+Arを用いて実行される,
ことを特徴とする請求項1に記載の半導体素子の製造方法。 - 基板上に非晶質シリコンを含むシリコンフィルムをLPCVD法又はPECVD法で蒸着する段階と;
前記シリコンフィルムを不純物でドーピングしてソース/ドレイン領域を定義する段階と;
前記非晶質シリコンをパターニングして半導体層を形成する段階と;
前記半導体層に上部に基板全面にかけてゲート絶縁膜を形成する段階と;
前記ゲート絶縁膜上部に前記半導体層のチャネル領域に対応するゲート電極を形成する段階;及び
H2O雰囲気,一定温度下で熱処理して前記非晶質シリコンを結晶化すると同時に不純物を活性化する段階;を含む,
ことを特徴とする半導体素子の製造方法。 - 前記一定温度は,550〜750℃の温度範囲にある,ことを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記一定温度は,600〜710℃の温度範囲にある,ことを特徴とする請求項10に記載の半導体素子の製造方法。
- 前記H2Oの圧力は,10,000Pa〜2MPaの圧力範囲にある,ことを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記シリコンフィルムの厚さは,2,000オングストローム以下である,ことを特徴とする請求項9に記載の半導体素子の製造方法。
- 前記シリコンフィルムの厚さは,300〜1,000オングストロームの範囲にある,ことを特徴とする請求項13に記載の半導体素子の製造方法。
- 前記PECVDは,330℃〜430℃の温度範囲で,1〜1.5Torrの圧力範囲で,SiH4+Ar及び/又はH2を用いて実行され,かつ,
前記LPCVDは,400〜500℃の温度範囲で,0.2〜0.4Torrの圧力範囲で,Si2H6+Arを用いて実行される,
ことを特徴とする請求項9に記載の半導体素子の製造方法。 - 基板上にゲート電極を形成する段階と;
前記ゲート電極上部に基板全面にかけてゲート絶縁膜を形成する段階と;
前記ゲート絶縁膜上部に非晶質シリコンを含むシリコンフィルムをLPCVD法又はPECVD法で蒸着する段階と;
フォトレジストを用いて不純物を前記シリコンフィルムに浸透させてソース/ドレイン領域を定義する段階と;
フォトレジストを除去した後H2O雰囲気,一定温度下で熱処理して前記非晶質シリコンを結晶化すると同時に不純物を活性化する段階;及び
ソース/ドレイン領域にソース/ドレイン電極をパターニングして形成する段階;を含む,
ことを特徴とする半導体素子の製造方法。 - 前記一定温度は,550〜750℃の温度範囲にある,ことを特徴とする請求項16に記載の半導体素子の製造方法。
- 前記一定温度は,600〜710℃の温度範囲にある,ことを特徴とする請求項17に記載の半導体素子の製造方法。
- 前記H2Oの圧力は,10,000Pa〜2MPaの圧力範囲にある,ことを特徴とする請求項16に記載の半導体素子の製造方法。
- 前記シリコンフィルムの厚さは,2,000オングストローム以下である,ことを特徴とする請求項16に記載の半導体素子の製造方法。
- 前記シリコンフィルムの厚さは,300〜1,000オングストロームの範囲にある,ことを特徴とする請求項20に記載の半導体素子の製造方法。
- 前記PECVDは,330℃〜430℃の温度範囲で,1〜1.5Torrの圧力範囲で,SiH4+Ar及び/又はH2を用いて実行され,かつ
前記LPCVDは,400〜500℃の温度範囲で,0.2〜0.4Torrの圧力範囲で,Si2H6+Arを用いて実行される,
ことを特徴とする請求項16に記載の半導体素子の製造方法。 - 前記請求項1の方法によって製造される半導体素子は,薄膜トランジスタである,
ことを特徴とする半導体素子。 - 前記薄膜トランジスタの半導体層を構成する多結晶シリコン薄膜のFWHMは,4.5〜7.5cm−1である,ことを特徴とする請求項23に記載の半導体素子。
- 前記薄膜トランジスタは,有機電界発光素子又は液晶表示素子に用いられるものである,ことを特徴とする請求項23に記載の半導体素子。
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US10319872B2 (en) | 2012-05-10 | 2019-06-11 | International Business Machines Corporation | Cost-efficient high power PECVD deposition for solar cells |
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JP3924828B2 (ja) | 1996-12-26 | 2007-06-06 | セイコーエプソン株式会社 | 結晶性半導体膜の製造方法、および薄膜トランジスタの製造方法 |
JPH10275913A (ja) * | 1997-03-28 | 1998-10-13 | Sanyo Electric Co Ltd | 半導体装置、半導体装置の製造方法及び薄膜トランジスタの製造方法 |
JPH11261078A (ja) | 1999-01-08 | 1999-09-24 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2000315794A (ja) | 1999-04-28 | 2000-11-14 | Ishikawajima Harima Heavy Ind Co Ltd | 薄膜トランジスタの製造方法。 |
JP2001210726A (ja) * | 2000-01-24 | 2001-08-03 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP4201239B2 (ja) | 2001-11-30 | 2008-12-24 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2004241397A (ja) * | 2003-01-23 | 2004-08-26 | Dainippon Printing Co Ltd | 薄膜トランジスタおよびその製造方法 |
KR100623251B1 (ko) * | 2004-02-19 | 2006-09-18 | 삼성에스디아이 주식회사 | 다결정 실리콘 박막의 제조 방법 및 이를 사용하여제조되는 다결정 실리콘을 사용하는 박막 트랜지스터 |
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CN1716552A (zh) | 2006-01-04 |
KR20060001706A (ko) | 2006-01-06 |
JP4188330B2 (ja) | 2008-11-26 |
CN100487878C (zh) | 2009-05-13 |
US7696030B2 (en) | 2010-04-13 |
KR100666552B1 (ko) | 2007-01-09 |
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