JP2005072563A - 半導体素子のゲート酸化膜形成方法 - Google Patents
半導体素子のゲート酸化膜形成方法 Download PDFInfo
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- JP2005072563A JP2005072563A JP2004191040A JP2004191040A JP2005072563A JP 2005072563 A JP2005072563 A JP 2005072563A JP 2004191040 A JP2004191040 A JP 2004191040A JP 2004191040 A JP2004191040 A JP 2004191040A JP 2005072563 A JP2005072563 A JP 2005072563A
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- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Abstract
【解決手段】 低電圧用トランジスタが形成される低電圧領域と、高電圧用トランジスタが形成される高電圧領域とが定義された、半導体基板の上部にパッド酸化膜及びパッド窒化膜を順次形成する段階と、前記高電圧領域が露出するようにすると共に、高電圧領域の半導体基板の所定の領域がリセスされるように前記結果物をパターニングする段階と、前記露出した高電圧領域に第1ゲート酸化膜を形成する段階と、前記第1ゲート酸化膜を除去する段階と、前記第1ゲート酸化膜の除去された高電圧領域に第2ゲート酸化膜を形成する段階と、前記結果物に形成されたパッド窒化膜及びパッド酸化膜を除去すると共に、高電圧領域の第2ゲート酸化膜の所定の深さがリセスされるようにエッチング工程を行う段階と、前記結果物の全面に第3ゲート酸化膜を形成する段階とを含む。
【選択図】 図5
Description
12 パッド酸化膜
14 パッド窒化膜
18a 第1ゲート酸化膜
18b 第2ゲート酸化膜
18c 第3ゲート酸化膜
Claims (5)
- 低電圧用トランジスタが形成される低電圧領域と、高電圧用トランジスタが形成される高電圧領域とが定義された、半導体基板上にパッド酸化膜及びパッド窒化膜を順次形成する段階と、
前記高電圧領域が露出するようにすると共に、高電圧領域の半導体基板の所定の領域がリセスされるように前記結果物をパターニングする段階と、
前記露出した高電圧領域に第1ゲート酸化膜を形成する段階と、
前記第1ゲート酸化膜を除去する段階と、
前記第1ゲート酸化膜の除去された高電圧領域に第2ゲート酸化膜を形成する段階と、
前記結果物に形成されたパッド窒化膜及びパッド酸化膜を除去すると共に、高電圧領域の第2ゲート酸化膜の所定の深さがリセスされるようにエッチング工程を行う段階と、
前記結果物の全面に第3ゲート酸化膜を形成する段階とを含む半導体素子のゲート酸化膜形成方法。 - 前記第1ゲート酸化膜は150〜1000Å程度の厚さにすることを特徴とする請求項1記載の半導体素子のゲート酸化膜形成方法。
- 前記第1ゲート酸化膜は、前記パターニング工程によって損傷された半導体基板を補償するために形成する犠牲酸化膜であることを特徴とする請求項1記載の半導体素子のゲート酸化膜形成方法。
- 前記第2ゲート酸化膜は150〜500Å程度の厚さにすることを特徴とする請求項1記載の半導体素子のゲート酸化膜形成方法。
- 前記第2ゲート酸化膜は、前記第3ゲート酸化膜と共に高電圧領域に形成される高電圧用トランジスタのゲート酸化膜になることを特徴とする請求項1記載の半導体素子のゲート酸化膜形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2003-59419 | 2003-08-27 | ||
KR10-2003-0059419A KR100481890B1 (ko) | 2003-08-27 | 2003-08-27 | 반도체소자의 게이트 산화막 형성방법 |
Publications (2)
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JP2005072563A true JP2005072563A (ja) | 2005-03-17 |
JP4741814B2 JP4741814B2 (ja) | 2011-08-10 |
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JP2004191040A Expired - Fee Related JP4741814B2 (ja) | 2003-08-27 | 2004-06-29 | 半導体素子のゲート酸化膜形成方法 |
Country Status (4)
Country | Link |
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US (1) | US7169670B2 (ja) |
JP (1) | JP4741814B2 (ja) |
KR (1) | KR100481890B1 (ja) |
TW (1) | TWI249780B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011077405A (ja) * | 2009-09-30 | 2011-04-14 | Toshiba Corp | 半導体装置及びその製造方法 |
KR20190115644A (ko) * | 2018-04-03 | 2019-10-14 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006012970A (ja) * | 2004-06-23 | 2006-01-12 | Toshiba Corp | 半導体装置およびその製造方法 |
US7205201B2 (en) * | 2004-08-09 | 2007-04-17 | System General Corp. | CMOS compatible process with different-voltage devices |
JP2009016706A (ja) * | 2007-07-09 | 2009-01-22 | Sony Corp | 半導体装置およびその製造方法 |
JP2009043897A (ja) * | 2007-08-08 | 2009-02-26 | Toshiba Corp | 半導体装置およびその製造方法 |
US8492228B1 (en) | 2012-07-12 | 2013-07-23 | International Business Machines Corporation | Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers |
US8921924B2 (en) | 2013-03-20 | 2014-12-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US9786563B2 (en) | 2015-11-23 | 2017-10-10 | International Business Machines Corporation | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer |
US10741569B2 (en) | 2017-06-30 | 2020-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001203285A (ja) * | 1999-12-24 | 2001-07-27 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2001257345A (ja) * | 2000-03-13 | 2001-09-21 | Nec Corp | 半導体装置の製造方法 |
JP2004111917A (ja) * | 2002-07-23 | 2004-04-08 | Toshiba Corp | 半導体装置及びその製造方法、不揮発性半導体記憶装置及びその製造方法、並びに不揮発性半導体記憶装置を備える電子装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000349164A (ja) * | 1999-06-08 | 2000-12-15 | Nec Corp | 素子分離絶縁膜を有する半導体装置の製造方法 |
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2003
- 2003-08-27 KR KR10-2003-0059419A patent/KR100481890B1/ko not_active IP Right Cessation
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2004
- 2004-06-29 JP JP2004191040A patent/JP4741814B2/ja not_active Expired - Fee Related
- 2004-06-30 US US10/880,691 patent/US7169670B2/en not_active Expired - Fee Related
- 2004-06-30 TW TW093119256A patent/TWI249780B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001203285A (ja) * | 1999-12-24 | 2001-07-27 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2001257345A (ja) * | 2000-03-13 | 2001-09-21 | Nec Corp | 半導体装置の製造方法 |
JP2004111917A (ja) * | 2002-07-23 | 2004-04-08 | Toshiba Corp | 半導体装置及びその製造方法、不揮発性半導体記憶装置及びその製造方法、並びに不揮発性半導体記憶装置を備える電子装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011077405A (ja) * | 2009-09-30 | 2011-04-14 | Toshiba Corp | 半導体装置及びその製造方法 |
KR20190115644A (ko) * | 2018-04-03 | 2019-10-14 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
KR102612021B1 (ko) | 2018-04-03 | 2023-12-11 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 |
Also Published As
Publication number | Publication date |
---|---|
US20050048723A1 (en) | 2005-03-03 |
KR100481890B1 (ko) | 2005-04-11 |
KR20050022593A (ko) | 2005-03-08 |
US7169670B2 (en) | 2007-01-30 |
TW200509230A (en) | 2005-03-01 |
JP4741814B2 (ja) | 2011-08-10 |
TWI249780B (en) | 2006-02-21 |
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