JP2004158021A - メモリ・ポート仲裁方法 - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
Abstract
【解決手段】 各装置に当初の優先度を割当てるステップと、第1装置がメモリ・ポートへのサービスをくり返し拒否されるときは第1優先度値よりも低い当初の優先度を有する第1装置に関して優先度を上げるステップと、第2装置がメモリ独占であることが決定されるときは第2優先度値よりも高い当初の優先度を有する第2装置に関して優先度を下げるステップと、第3装置によって発せられる未決のメモリ・アクセス要求によりアドレスされる行がMAUによりサービスを受けた先行メモリ・アクセス要求によりアドレスされる行に対応するときは第3装置に関して優先度を上げるステップと、優先度に従って各装置により発せられるメモリ・ポートのための要求をサービスするステップとを有する。
【選択図】 図2
Description
1.発明の名称「高性能RISCマイクロプロセッサ・ア−キテクチャ」(High−Performance RISC Microprocessor Architecture)SMOS−7984MCF/GBR,米国特許出願第07/727,006号、1991年7月8日出願、発明者Le T.Nguyen他、およびこれに対応する特願平5−502150(特表平6−501122号公報)。
2.発明の名称「拡張可能RISCマイクロプロセッサ・アーキテクチヤ」(Extensible RISC Microprocessor Architecture)SMOS−7985MCF/GBR,米国特許出願第07/727,058号、1991年7月8日出願、発明者Le T.Nguyen他、およびこれに対応する特願平5−502153(特表平6−501124号公報)。
3.「アーキテクチャ上の依存関係を隔離したRISCマイクロプロセッサ・アーキテクチャ」(RISC Microprocessor Architecture with Isolated Architectura Dependencies)SMOS−7987MCF/GBR/RCC,米題特許出願第07/726,744号、1991年7月8日出願、発明者Le T.Nguyen他、およびこれに対応する特願平5−502152(特表平6−502034号公報)。
4.発明の名称「複数型レジスタ・セットを採用したRISCマイクロプロセッサ・アーキテクチャ」(RISC Microprocessor Architecture Implementing Multiple Typed Register Sets)SMOS−7988MCF/GBR/RCC,米国特許出願第07/726,773号、1991年7月8日出願、発明者Sanjiv Garg他、およびこれに対応する特願平5−502403(特表平6−501805号公報)。
5.発明の名称「高速トラップと例外状態をインプリメントしたRISCマイクロプロセッサ・アーキテクチャ」(RISC Microprocessor Architecture Impiementing FaSt Trap and Exception State)SMOS−7989MCF/GBR/WSW,米国特許出願第07/726,942号、1991年7月8日出願、発明者Le T.Nguyen他、およびこれに対応する特願平5−502154(特表平6−502035号公報)。
6.発明の名称「シングル・チップ・ページ・プリンタ・コントローラ」(Single Chip Page Printer Controller)SMOS−7991MCF/GBR/HKW,米国特許出願第07/726,929号、1991年7月8日出願、発明者Derek J.Lentz他、およびこれに対応する特願平5−502149(特表平6−501586号公報)。
関連技術の説明
複数のプロセッサをサポートできるマイクロプロセッサ・アーキテクチャを有するコンピュータ・システムは、メモリと、データ・バス、アドレス・バスおよび制御信号バスからなるメモリ・システム・バスと、データ・バス、アドレス・バスおよび制御信号バスからなる入出力(I/O)バスと、複数の入出力デバイスと、複数のマイクロプロセッサとを備えているのが代表的である。入出力デバイスは、例えば、直接メモリ・アクセス(DMA)コントローラ・プロセッサ、イーサネット(ETHERNET)チップ、その他の各種入出力デバイスで構成されている。マイクロプロセッサは、例えば、複数の汎用プロセッサと特殊用途のプロセッサとから構成されている。これらのプロセッサはメモリ・システム・バスを介してメモリに接続され、入出力バスを介して入出力デバイスに接続されている。
2.要求したアドレスは以前にサービスを受けた要求と行が一致するか
3.そのデバイスは余りにも多くの回数サービスを受けることが拒否されたか 4.そのマスタは余りにも多くの回数サービスを受けたか
デバイスからの各要求は固有の優先度をもっている。IOUは優先度が最も高く、そのあとにIキャッシュとDキャッシュが続く。しかし、下述するように、Dキャッシュからの介入(intervention−ITV)要求は、スレーブ側処理エレメント(processing element−PE)が更新データをできる限り早く受け取る必要があるために、すべての中で優先度が最も高くなっている。
2.Iキャッシュ
3.IOU
スレーブ・デバイスとなり得るものには、次のものがある。
2.IOU
スイッチ・ネットワーク54は、必要な介入要求を該当するポート・インタフェースヘ送って、実行させることを担当する。
SW IDBST〔3:0〕は、識別(ID)コードとバンク開始コードをスレーブ・デバイスからマスタ・デバイスヘバス88を経由して返すために使用される。スレーブ・デバイスからのデータは常に順番に返されるので、一般的にはIDをポートまで送る必要はない。IDは、インタフェース内の各ポートごとに1つあて用意されている個々のFIFOにストアしておくことができる。
上述したように、3つのマスタと、MCUのサービスを受ける2つの資源が存在する。3つのマスタとは、Dキャッシュ、IキャッシュおよびIOUである。2つの資源、つまり、スレーブはメモリ・ポートとIOUである。上から明らかなように、IOUはマスタと資源/スレーブの両方になることができる。
2.要求したアドレスと以前にサービスを受けた要求のアドレスとが行一致している
3.デバイスは余りにも多くの回数サービスを拒否されてきた
4.マスタは余りにも多くの回数サービスを受けてきた
図7に示すように、メモリ・ポートを要求するときに使用される動的優先度方式は次のとおりである。
デバイスからの各要求は固有優先度をもっている。IOUが高優先度または通常優先度を要求することができ、次にDキャッシュが、その次にIキャッシュが要求できる。しかし、Dキャッシュからの介入(ITV)要求がすべての中で最も優先度が高くなっている。
2.優先度がマスタまたは要求側デバイス(すなわち、IOU、DキャッシュおよびIキャッシュ)を基準にしているマスタ優先度方式
スレーブ優先度方式では、優先度は常にラウンド・ロビン方式でメモリ・ポートに与えられる。つまり、優先度は最初にメモリ・ポート0、1、2...に与えられ、次にIOUに与えられる。これに対して、マスタ優先度方式では、優先度は最初にIOUに与えられ、次にDキャッシュとIキャッシュに与えられる。勿論、事情によっては、マスタ優先方式に従ってITV要求に最高優先度を与える必要がある場合やそうした方が望ましい場合がある。また、プリフェッチ・バッファがやがて空になる場合に、Iキャッシュに高優先度を与える必要がある場合やそうしたほうが望ましい場合がある。いずれの場合も、使用する優先度方式は、様々な動作条件に合うようにソフトウェアで調整することが可能である。
Claims (2)
- メモリ・アレイ・ユニット(MAU)と、前記MAUに結合された複数のメモリ・ポートと、前記メモリ・ポートを通じて前記MAUにアクセスする複数の装置を有するコンピュータ・システムにおいて、前記メモリ・ポートのため仲裁を行うメモリ・ポート仲裁方法であって、
(1)前記各装置に優先度を割当てるステップと、
(2)前記優先度に従って前記各装置により発せられる前記メモリ・ポートのための要求をサービスするステップとを有し、
ステップ(1)は、
(a)前記装置のそれぞれに当初の優先度を割当てるステップと、
(b)第1装置がメモリ・ポートへのサービスをくり返し拒否されるときは、第1優先度値よりも低い当初の優先度を有する第1装置に関して優先度を上げるステップと、
(c)第2装置がメモリ独占であることが決定されるときは、第2優先度値よりも高い当初の優先度を有する第2装置に関して優先度を下げるステップと、
(d)第3装置によって発せられる未決のメモリ・アクセス要求によりアドレスされる行が、前記MAUによりサービスを受けた先行メモリ・アクセス要求によりアドレスされる行に対応するときは、第3装置に関して優先度を上げるステップと
を有することを特徴とするメモリ・ポート仲裁方法。 - 前記ステップ(c)は、
中断のあと前記第2装置がはじめてサービスを受けるときは、カウンタを所定の値に初期化するステップと、
前記第2装置が中断なしにサービスを受けるたびに前記カウンタの数を減じるステップと、
前記カウンタがゼロに達するときは、前記第2装置がメモリ独占であることを決定するステップと
を有することを特徴とする請求項1記載のメモリ・ポート仲裁方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/726,893 US5440752A (en) | 1991-07-08 | 1991-07-08 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50215193A Division JP3557617B2 (ja) | 1991-07-08 | 1992-07-07 | 複数の異種プロセッサをサポートすることのできるマイクロプロセッサ・アーキテクチャ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004158021A true JP2004158021A (ja) | 2004-06-03 |
JP3850829B2 JP3850829B2 (ja) | 2006-11-29 |
Family
ID=24920467
Family Applications (7)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50215193A Expired - Fee Related JP3557617B2 (ja) | 1991-07-08 | 1992-07-07 | 複数の異種プロセッサをサポートすることのできるマイクロプロセッサ・アーキテクチャ |
JP2003406721A Expired - Lifetime JP3632766B2 (ja) | 1991-07-08 | 2003-12-05 | プロセッサ・システム |
JP2003406723A Expired - Lifetime JP3850829B2 (ja) | 1991-07-08 | 2003-12-05 | メモリ・ポート仲裁方法 |
JP2003406720A Expired - Lifetime JP3624951B2 (ja) | 1991-07-08 | 2003-12-05 | マルチプロセッサ・システム |
JP2003406722A Expired - Lifetime JP3624952B2 (ja) | 1991-07-08 | 2003-12-05 | データ転送方法 |
JP2004265076A Withdrawn JP2005050368A (ja) | 1991-07-08 | 2004-09-13 | マルチプロセッサ・システム |
JP2004265075A Expired - Fee Related JP3687750B2 (ja) | 1991-07-08 | 2004-09-13 | マルチプロセッサ・システム |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50215193A Expired - Fee Related JP3557617B2 (ja) | 1991-07-08 | 1992-07-07 | 複数の異種プロセッサをサポートすることのできるマイクロプロセッサ・アーキテクチャ |
JP2003406721A Expired - Lifetime JP3632766B2 (ja) | 1991-07-08 | 2003-12-05 | プロセッサ・システム |
Family Applications After (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003406720A Expired - Lifetime JP3624951B2 (ja) | 1991-07-08 | 2003-12-05 | マルチプロセッサ・システム |
JP2003406722A Expired - Lifetime JP3624952B2 (ja) | 1991-07-08 | 2003-12-05 | データ転送方法 |
JP2004265076A Withdrawn JP2005050368A (ja) | 1991-07-08 | 2004-09-13 | マルチプロセッサ・システム |
JP2004265075A Expired - Fee Related JP3687750B2 (ja) | 1991-07-08 | 2004-09-13 | マルチプロセッサ・システム |
Country Status (8)
Country | Link |
---|---|
US (9) | US5440752A (ja) |
EP (3) | EP0886225B1 (ja) |
JP (7) | JP3557617B2 (ja) |
KR (1) | KR100248902B1 (ja) |
AT (3) | ATE177221T1 (ja) |
DE (3) | DE69233655T2 (ja) |
HK (2) | HK1012742A1 (ja) |
WO (1) | WO1993001553A1 (ja) |
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