JP2004153269A - 基板貫通の相互接続部を形成する方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/0001—Technical content checked by a classifier
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Abstract
【解決手段】表側と裏側を有する基板(30)を含むマイクロエレクトロニクス・デバイス用の基板貫通の相互接続部(42)を形成する方法(10)を提供する。この方法は、前記基板(30)の前記表側に回路素子(34)を形成するステップと、前記回路素子(34)に達するトレンチ(38)を前記基板の前記裏側に形成するステップと、ポリマー絶縁材料の一層(40)を前記トレンチ(38)内に形成するステップと、前記回路素子(34)を少なくとも一部露出させるに足るポリマー材料を、前記ポリマー絶縁材料の前記層(40)から除去するステップと、前記回路素子(34)と電気的に通じている導電相互接続層(42)を前記トレンチ(38)内に形成するステップと、を有する。
【選択図】 図6
Description
を有する方法(10)。
34 回路要素
38 トレンチ
40 ポリマー絶縁材料の層
42 基板貫通の相互接続層
44 フィラー層
Claims (10)
- 表側と裏側を有する基板を含むマイクロエレクトロニクス・デバイス用の基板貫通の相互接続部を形成する方法であって、
前記基板の前記表側に回路素子を形成するステップと、
前記回路素子に達するトレンチを前記基板の前記裏側に形成するステップと、
ポリマー絶縁材料の一層を前記トレンチ内に形成するステップと、
前記回路素子を少なくとも一部露出させるに足るポリマー材料を、前記ポリマー絶縁材料の前記層から除去するステップと、
前記回路素子と電気的に通じている導電相互接続層を前記トレンチ内に形成するステップと、
を有する方法。 - 前記トレンチを前記基板の裏側に形成するステップは、レーザ・アブレーションと深い反応性イオン・エッチングから成るグループから選択された技法によって前記トレンチを形成するステップを有することを特徴とする請求項1に記載の方法。
- ポリマー絶縁材料の前記層を前記トレンチ内に形成するステップは、パリレンの一層を前記トレンチ内に形成するステップを有することを特徴とする請求項1に記載の方法。
- パリレンの前記層を前記トレンチ内に形成した後で、前記基板を約300°Cまで加熱して、パリレンの前記層の外部領域内に拡散バリヤ層を形成するステップをさらに有することを特徴とする請求項3に記載の方法。
- フィラー層を、前記トレンチ内で、前記導電相互接続層の上に形成するステップをさらに有することを特徴とする請求項1に記載の方法。
- 前記フィラー層は、パリレンから形成されることを特徴とする請求項5に記載の方法。
- 前記フィラー層は、導電材料から形成されることを特徴とする請求項5に記載の方法。
- 表側と裏側を有する基板を含むマイクロエレクトロニクス・デバイス用の基板貫通の相互接続部を形成する方法であって、
前記基板の前記表側に導電回路素子を形成するステップと、
前記回路素子に達する、内面を含むトレンチを前記基板裏側に形成するステップと、
前記回路素子の少なくとも一部を、前記トレンチを通じて露出させるように、パリレンの一層を前記トレンチの前記内面に形成するステップと、
前記回路素子と電気的に通じている導電相互接続層をパリレンの前記層内に形成するステップと、
を有する方法。 - 表側、裏側、バルク領域を有する基板と、
前記基板の前記表側に形成された回路素子と、
前記基板の前記裏側から、前記基板の前記表側へ、前記基板の前記バルク領域を貫通している基板貫通の相互接続部と、
を備え、
前記基板貫通の相互接続部は、ポリマー誘電体層によって、前記基板の前記バルク領域から隔てられる導電相互接続層を有することを特徴とするマイクロエレクトロニクス・デバイス。 - 表側と、裏側と、および、電流を基板の前記裏側から、前記基板を通って前記基板の前記表側に形成された回路素子へ流すように構成された基板貫通の相互接続部とを有する基板を含む、流体受取り媒体上に流体を噴出するように構成された流体噴出ヘッドを備える流体噴出カートリッジであって、
前記基板貫通の相互接続部は、
前記基板を貫通するトレンチと、
前記トレンチ内に形成されたポリマー誘電体材料の一層と、
前記トレンチ内で、ポリマー誘電体材料の前記層の上に形成された導電体の一層であって、前記回路素子と電気的に通じている導電体の一層と、
を具備する流体噴出カートリッジ。
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US10/286,060 US6790775B2 (en) | 2002-10-31 | 2002-10-31 | Method of forming a through-substrate interconnect |
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JP (2) | JP2004153269A (ja) |
CN (1) | CN100345275C (ja) |
DE (1) | DE10331819A1 (ja) |
TW (1) | TWI260737B (ja) |
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Also Published As
Publication number | Publication date |
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DE10331819A1 (de) | 2004-05-27 |
CN1499607A (zh) | 2004-05-26 |
TW200406872A (en) | 2004-05-01 |
CN100345275C (zh) | 2007-10-24 |
US20040087126A1 (en) | 2004-05-06 |
JP5548162B2 (ja) | 2014-07-16 |
US6790775B2 (en) | 2004-09-14 |
TWI260737B (en) | 2006-08-21 |
JP2011187992A (ja) | 2011-09-22 |
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