JP2003050269A5 - - Google Patents

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Publication number
JP2003050269A5
JP2003050269A5 JP2002117030A JP2002117030A JP2003050269A5 JP 2003050269 A5 JP2003050269 A5 JP 2003050269A5 JP 2002117030 A JP2002117030 A JP 2002117030A JP 2002117030 A JP2002117030 A JP 2002117030A JP 2003050269 A5 JP2003050269 A5 JP 2003050269A5
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JP
Japan
Prior art keywords
bit
register
trigger
value
trigger signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002117030A
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English (en)
Japanese (ja)
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JP4298960B2 (ja
JP2003050269A (ja
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Publication date
Priority claimed from US09/838,766 external-priority patent/US6834364B2/en
Application filed filed Critical
Publication of JP2003050269A publication Critical patent/JP2003050269A/ja
Publication of JP2003050269A5 publication Critical patent/JP2003050269A5/ja
Application granted granted Critical
Publication of JP4298960B2 publication Critical patent/JP4298960B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2002117030A 2001-04-19 2002-04-19 アルゴリズム的にプログラム可能なメモリテスタにおけるトリガ信号生成方法 Expired - Fee Related JP4298960B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/838766 2001-04-19
US09/838,766 US6834364B2 (en) 2001-04-19 2001-04-19 Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences

Publications (3)

Publication Number Publication Date
JP2003050269A JP2003050269A (ja) 2003-02-21
JP2003050269A5 true JP2003050269A5 (https=) 2005-09-22
JP4298960B2 JP4298960B2 (ja) 2009-07-22

Family

ID=25277994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002117030A Expired - Fee Related JP4298960B2 (ja) 2001-04-19 2002-04-19 アルゴリズム的にプログラム可能なメモリテスタにおけるトリガ信号生成方法

Country Status (4)

Country Link
US (1) US6834364B2 (https=)
JP (1) JP4298960B2 (https=)
KR (1) KR100881843B1 (https=)
DE (1) DE10217303A1 (https=)

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US6763490B1 (en) * 2000-09-25 2004-07-13 Agilent Technologies, Inc. Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester
US20020199179A1 (en) * 2001-06-21 2002-12-26 Lavery Daniel M. Method and apparatus for compiler-generated triggering of auxiliary codes
US7793191B2 (en) * 2002-04-05 2010-09-07 Sony Corporation Interleave device, interleaving method, deinterleave device, and deinterleave method
US7178135B2 (en) * 2002-05-16 2007-02-13 International Business Machines Corporation Scope-based breakpoint selection and operation
US20040019828A1 (en) * 2002-07-25 2004-01-29 Gergen Joseph P. Method and apparatus for debugging a data processing system
US20040025083A1 (en) * 2002-07-31 2004-02-05 Murthi Nanja Generating test code for software
US7509533B1 (en) * 2003-06-30 2009-03-24 Sun Microsystems, Inc. Methods and apparatus for testing functionality of processing devices by isolation and testing
JP4737929B2 (ja) * 2003-12-12 2011-08-03 株式会社東芝 半導体記憶装置
US7216256B2 (en) * 2004-03-30 2007-05-08 Bellsouth Intellectual Property Corporation Methods, systems, and products for verifying integrity of web-server served content
US7426556B2 (en) * 2004-03-30 2008-09-16 At&T Intellectual Property I, L.P. Methods, systems, and products for verifying integrity of web-server served content
US7363364B2 (en) * 2004-03-30 2008-04-22 At&T Delaware Intellectual Property, Inc. Methods, systems, and products for verifying integrity of web-server served content
US7353437B2 (en) 2004-10-29 2008-04-01 Micron Technology, Inc. System and method for testing a memory for a memory failure exhibited by a failing memory
JPWO2007043144A1 (ja) * 2005-10-05 2009-04-16 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 負荷試験装置およびその方法
DE102005048872A1 (de) * 2005-10-12 2007-04-26 Mühlbauer Ag Testkopfeinrichtung
US7650555B2 (en) * 2006-07-27 2010-01-19 International Business Machines Corporation Method and apparatus for characterizing components of a device under test using on-chip trace logic analyzer
KR100764052B1 (ko) * 2006-08-03 2007-10-08 삼성전자주식회사 유동적 어드레스 바운더리를 갖는 플래시 메모리 장치 및그것의 프로그램 방법
US7680621B2 (en) * 2007-08-15 2010-03-16 Keithley Instruments, Inc. Test instrument network
JP2009300248A (ja) * 2008-06-13 2009-12-24 Mitsubishi Electric Corp 並列試験装置
KR20100103212A (ko) * 2009-03-13 2010-09-27 삼성전자주식회사 복수개의 테스트 모듈을 구비하는 테스트 보드 및 이를 구비하는 테스트 시스템
US8683456B2 (en) 2009-07-13 2014-03-25 Apple Inc. Test partitioning for a non-volatile memory
US8650446B2 (en) * 2010-03-24 2014-02-11 Apple Inc. Management of a non-volatile memory based on test quality
US8645776B2 (en) * 2010-03-24 2014-02-04 Apple Inc. Run-time testing of memory locations in a non-volatile memory
US8751903B2 (en) 2010-07-26 2014-06-10 Apple Inc. Methods and systems for monitoring write operations of non-volatile memory
US9397500B2 (en) * 2013-06-28 2016-07-19 Solantro Semiconductor Corp. Inverter with extended endurance memory
CN110502439B (zh) * 2019-08-07 2024-01-12 Oppo广东移动通信有限公司 调试方法、装置、电子设备以及存储介质
CN114218032B (zh) * 2021-11-30 2026-01-23 山东云海国创云计算装备产业创新中心有限公司 一种硬件设计验证方法、装置及电子设备和存储介质
CN114218879B (zh) * 2021-12-13 2026-02-06 海光信息技术股份有限公司 用于验证的寄存器随机方法、系统、设备以及存储介质
CN114444537B (zh) * 2021-12-20 2025-06-10 北京电子工程总体研究所 一种测试数据自动判读系统和方法
CN114546822A (zh) * 2021-12-27 2022-05-27 芯华章科技股份有限公司 测试设计的方法、电子设备及存储介质
US11914500B2 (en) 2022-02-03 2024-02-27 Apple Inc. Debugging of accelerator circuit for mathematical operations using packet limit breakpoint
US12205660B2 (en) * 2022-11-08 2025-01-21 SanDisk Technologies, Inc. Test controller enabling a snapshot restore and resume operation within a device under test
US12374417B2 (en) 2022-11-10 2025-07-29 Intelligent Memory Limited Apparatus, systems, and methods for dynamically reconfigured semiconductor tester for volatile and non-volatile memories
US20250308578A1 (en) * 2024-04-02 2025-10-02 Nanya Technology Corporation Data verification device and data verification method

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JP2577120Y2 (ja) * 1993-04-15 1998-07-23 株式会社アドバンテスト 過剰パルス印加の禁止回路
JP3237473B2 (ja) * 1995-06-29 2001-12-10 安藤電気株式会社 マスク制御装置
JP3846939B2 (ja) * 1995-08-30 2006-11-15 フリースケール セミコンダクター インコーポレイテッド データプロセッサ
US5771240A (en) * 1996-11-14 1998-06-23 Hewlett-Packard Company Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin
US6360340B1 (en) * 1996-11-19 2002-03-19 Teradyne, Inc. Memory tester with data compression
US6253338B1 (en) * 1998-12-21 2001-06-26 International Business Machines Corporation System for tracing hardware counters utilizing programmed performance monitor to generate trace interrupt after each branch instruction or at the end of each code basic block
US6327544B1 (en) * 1999-03-01 2001-12-04 Agilent Technologies, Inc. Automatic storage of a trigger definition in a signal measurement system
DE69940061D1 (de) * 1999-09-30 2009-01-22 St Microelectronics Srl Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit
US6615369B1 (en) * 2000-01-31 2003-09-02 Agilent Technologies, Inc. Logic analyzer with trigger specification defined by waveform exemplar

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