JP4298960B2 - アルゴリズム的にプログラム可能なメモリテスタにおけるトリガ信号生成方法 - Google Patents

アルゴリズム的にプログラム可能なメモリテスタにおけるトリガ信号生成方法 Download PDF

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JP4298960B2
JP4298960B2 JP2002117030A JP2002117030A JP4298960B2 JP 4298960 B2 JP4298960 B2 JP 4298960B2 JP 2002117030 A JP2002117030 A JP 2002117030A JP 2002117030 A JP2002117030 A JP 2002117030A JP 4298960 B2 JP4298960 B2 JP 4298960B2
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test
trigger
bit
memory
register
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JP2003050269A5 (https=
JP2003050269A (ja
Inventor
アラン・エス・クレッチ・ジュニア
ブラッド・ディ・リーク
ランディ・エル・ベイリー
ジョン・エム・フリースマン
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Verigy Singapore Pte Ltd
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Verigy Singapore Pte Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2002117030A 2001-04-19 2002-04-19 アルゴリズム的にプログラム可能なメモリテスタにおけるトリガ信号生成方法 Expired - Fee Related JP4298960B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/838766 2001-04-19
US09/838,766 US6834364B2 (en) 2001-04-19 2001-04-19 Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences

Publications (3)

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JP2003050269A JP2003050269A (ja) 2003-02-21
JP2003050269A5 JP2003050269A5 (https=) 2005-09-22
JP4298960B2 true JP4298960B2 (ja) 2009-07-22

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JP2002117030A Expired - Fee Related JP4298960B2 (ja) 2001-04-19 2002-04-19 アルゴリズム的にプログラム可能なメモリテスタにおけるトリガ信号生成方法

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US (1) US6834364B2 (https=)
JP (1) JP4298960B2 (https=)
KR (1) KR100881843B1 (https=)
DE (1) DE10217303A1 (https=)

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US7363364B2 (en) * 2004-03-30 2008-04-22 At&T Delaware Intellectual Property, Inc. Methods, systems, and products for verifying integrity of web-server served content
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JPWO2007043144A1 (ja) * 2005-10-05 2009-04-16 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 負荷試験装置およびその方法
DE102005048872A1 (de) * 2005-10-12 2007-04-26 Mühlbauer Ag Testkopfeinrichtung
US7650555B2 (en) * 2006-07-27 2010-01-19 International Business Machines Corporation Method and apparatus for characterizing components of a device under test using on-chip trace logic analyzer
KR100764052B1 (ko) * 2006-08-03 2007-10-08 삼성전자주식회사 유동적 어드레스 바운더리를 갖는 플래시 메모리 장치 및그것의 프로그램 방법
US7680621B2 (en) * 2007-08-15 2010-03-16 Keithley Instruments, Inc. Test instrument network
JP2009300248A (ja) * 2008-06-13 2009-12-24 Mitsubishi Electric Corp 並列試験装置
KR20100103212A (ko) * 2009-03-13 2010-09-27 삼성전자주식회사 복수개의 테스트 모듈을 구비하는 테스트 보드 및 이를 구비하는 테스트 시스템
US8683456B2 (en) 2009-07-13 2014-03-25 Apple Inc. Test partitioning for a non-volatile memory
US8650446B2 (en) * 2010-03-24 2014-02-11 Apple Inc. Management of a non-volatile memory based on test quality
US8645776B2 (en) * 2010-03-24 2014-02-04 Apple Inc. Run-time testing of memory locations in a non-volatile memory
US8751903B2 (en) 2010-07-26 2014-06-10 Apple Inc. Methods and systems for monitoring write operations of non-volatile memory
US9397500B2 (en) * 2013-06-28 2016-07-19 Solantro Semiconductor Corp. Inverter with extended endurance memory
CN110502439B (zh) * 2019-08-07 2024-01-12 Oppo广东移动通信有限公司 调试方法、装置、电子设备以及存储介质
CN114218032B (zh) * 2021-11-30 2026-01-23 山东云海国创云计算装备产业创新中心有限公司 一种硬件设计验证方法、装置及电子设备和存储介质
CN114218879B (zh) * 2021-12-13 2026-02-06 海光信息技术股份有限公司 用于验证的寄存器随机方法、系统、设备以及存储介质
CN114444537B (zh) * 2021-12-20 2025-06-10 北京电子工程总体研究所 一种测试数据自动判读系统和方法
CN114546822A (zh) * 2021-12-27 2022-05-27 芯华章科技股份有限公司 测试设计的方法、电子设备及存储介质
US11914500B2 (en) 2022-02-03 2024-02-27 Apple Inc. Debugging of accelerator circuit for mathematical operations using packet limit breakpoint
US12205660B2 (en) * 2022-11-08 2025-01-21 SanDisk Technologies, Inc. Test controller enabling a snapshot restore and resume operation within a device under test
US12374417B2 (en) 2022-11-10 2025-07-29 Intelligent Memory Limited Apparatus, systems, and methods for dynamically reconfigured semiconductor tester for volatile and non-volatile memories
US20250308578A1 (en) * 2024-04-02 2025-10-02 Nanya Technology Corporation Data verification device and data verification method

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JP3237473B2 (ja) * 1995-06-29 2001-12-10 安藤電気株式会社 マスク制御装置
JP3846939B2 (ja) * 1995-08-30 2006-11-15 フリースケール セミコンダクター インコーポレイテッド データプロセッサ
US5771240A (en) * 1996-11-14 1998-06-23 Hewlett-Packard Company Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin
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US6615369B1 (en) * 2000-01-31 2003-09-02 Agilent Technologies, Inc. Logic analyzer with trigger specification defined by waveform exemplar

Also Published As

Publication number Publication date
KR100881843B1 (ko) 2009-02-03
US6834364B2 (en) 2004-12-21
DE10217303A1 (de) 2002-10-31
JP2003050269A (ja) 2003-02-21
US20020157042A1 (en) 2002-10-24
KR20020081673A (ko) 2002-10-30

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