JP2002538625A - 部分的にゲル状態に加熱されたアンダーフィル材料を有する制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス - Google Patents

部分的にゲル状態に加熱されたアンダーフィル材料を有する制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス

Info

Publication number
JP2002538625A
JP2002538625A JP2000603089A JP2000603089A JP2002538625A JP 2002538625 A JP2002538625 A JP 2002538625A JP 2000603089 A JP2000603089 A JP 2000603089A JP 2000603089 A JP2000603089 A JP 2000603089A JP 2002538625 A JP2002538625 A JP 2002538625A
Authority
JP
Japan
Prior art keywords
integrated circuit
substrate
underfill material
package
attaching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000603089A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002538625A5 (https=
Inventor
クック，デュエーン
ムラーリ，ヴェンカトゥサン
ラマリンガム，スレシュ
ボドラハーリ，ナゲシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2002538625A publication Critical patent/JP2002538625A/ja
Publication of JP2002538625A5 publication Critical patent/JP2002538625A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2000603089A 1999-03-03 2000-02-08 部分的にゲル状態に加熱されたアンダーフィル材料を有する制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス Pending JP2002538625A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/261,648 US6331446B1 (en) 1999-03-03 1999-03-03 Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US09/261,648 1999-03-03
PCT/US2000/003244 WO2000052752A2 (en) 1999-03-03 2000-02-08 A process for underfilling flip-chip integrated circuit package with an underfill material that is heated to a partial gel state

Publications (2)

Publication Number Publication Date
JP2002538625A true JP2002538625A (ja) 2002-11-12
JP2002538625A5 JP2002538625A5 (https=) 2007-03-08

Family

ID=22994229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000603089A Pending JP2002538625A (ja) 1999-03-03 2000-02-08 部分的にゲル状態に加熱されたアンダーフィル材料を有する制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス

Country Status (7)

Country Link
US (1) US6331446B1 (https=)
JP (1) JP2002538625A (https=)
KR (1) KR100443732B1 (https=)
CN (1) CN1157782C (https=)
AU (1) AU2986200A (https=)
MX (1) MXPA01008692A (https=)
WO (1) WO2000052752A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12507513B2 (en) 2022-07-13 2025-12-23 Nichia Corporation Method for manufacturing light-emitting device, and light-emitting device

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US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6545869B2 (en) * 2001-01-17 2003-04-08 International Business Machines Corporation Adjusting fillet geometry to couple a heat spreader to a chip carrier
TW502422B (en) * 2001-06-07 2002-09-11 Ultra Tera Corp Method for encapsulating thin flip-chip-type semiconductor device
US20030129438A1 (en) * 2001-12-14 2003-07-10 Becker Kevin Harris Dual cure B-stageable adhesive for die attach
US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US6979600B2 (en) * 2004-01-06 2005-12-27 Intel Corporation Apparatus and methods for an underfilled integrated circuit package
US9373559B2 (en) * 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
US10037900B1 (en) 2017-05-09 2018-07-31 Nxp B.V. Underfill stop using via bars in semiconductor packages
KR102477352B1 (ko) 2017-09-29 2022-12-15 삼성전자주식회사 반도체 패키지 및 이미지 센서
CN113113325A (zh) * 2021-04-08 2021-07-13 中国电子科技集团公司第二十四研究所 多芯片倒装焊三层封装结构的底填灌封方法

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JPH10112476A (ja) * 1996-10-04 1998-04-28 Fuji Xerox Co Ltd 半導体装置の製造方法
JPH10223686A (ja) * 1997-02-05 1998-08-21 Nec Corp 半導体実装方法

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JPH08153830A (ja) * 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
JPH10112476A (ja) * 1996-10-04 1998-04-28 Fuji Xerox Co Ltd 半導体装置の製造方法
JPH10223686A (ja) * 1997-02-05 1998-08-21 Nec Corp 半導体実装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12507513B2 (en) 2022-07-13 2025-12-23 Nichia Corporation Method for manufacturing light-emitting device, and light-emitting device

Also Published As

Publication number Publication date
US6331446B1 (en) 2001-12-18
KR20020005611A (ko) 2002-01-17
WO2000052752A2 (en) 2000-09-08
CN1354888A (zh) 2002-06-19
WO2000052752A3 (en) 2001-03-08
CN1157782C (zh) 2004-07-14
MXPA01008692A (es) 2002-03-14
AU2986200A (en) 2000-09-21
KR100443732B1 (ko) 2004-08-09

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