AU2986200A - A process for underfilling a controlled collapse chip connection (c4) integratedcircuit package with an underfill material that is heated to a partial gel stat - Google Patents

A process for underfilling a controlled collapse chip connection (c4) integratedcircuit package with an underfill material that is heated to a partial gel stat

Info

Publication number
AU2986200A
AU2986200A AU29862/00A AU2986200A AU2986200A AU 2986200 A AU2986200 A AU 2986200A AU 29862/00 A AU29862/00 A AU 29862/00A AU 2986200 A AU2986200 A AU 2986200A AU 2986200 A AU2986200 A AU 2986200A
Authority
AU
Australia
Prior art keywords
integratedcircuit
underfilling
stat
package
heated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU29862/00A
Other languages
English (en)
Inventor
Duane Cook
Venkatesan Murali
Suresh Ramalingam
Nagesh Vodrahalli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2986200A publication Critical patent/AU2986200A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
AU29862/00A 1999-03-03 2000-02-08 A process for underfilling a controlled collapse chip connection (c4) integratedcircuit package with an underfill material that is heated to a partial gel stat Abandoned AU2986200A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09261648 1999-03-03
US09/261,648 US6331446B1 (en) 1999-03-03 1999-03-03 Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
PCT/US2000/003244 WO2000052752A2 (en) 1999-03-03 2000-02-08 A process for underfilling flip-chip integrated circuit package with an underfill material that is heated to a partial gel state

Publications (1)

Publication Number Publication Date
AU2986200A true AU2986200A (en) 2000-09-21

Family

ID=22994229

Family Applications (1)

Application Number Title Priority Date Filing Date
AU29862/00A Abandoned AU2986200A (en) 1999-03-03 2000-02-08 A process for underfilling a controlled collapse chip connection (c4) integratedcircuit package with an underfill material that is heated to a partial gel stat

Country Status (7)

Country Link
US (1) US6331446B1 (https=)
JP (1) JP2002538625A (https=)
KR (1) KR100443732B1 (https=)
CN (1) CN1157782C (https=)
AU (1) AU2986200A (https=)
MX (1) MXPA01008692A (https=)
WO (1) WO2000052752A2 (https=)

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* Cited by examiner, † Cited by third party
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US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6545869B2 (en) * 2001-01-17 2003-04-08 International Business Machines Corporation Adjusting fillet geometry to couple a heat spreader to a chip carrier
TW502422B (en) * 2001-06-07 2002-09-11 Ultra Tera Corp Method for encapsulating thin flip-chip-type semiconductor device
US20030129438A1 (en) * 2001-12-14 2003-07-10 Becker Kevin Harris Dual cure B-stageable adhesive for die attach
US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US6979600B2 (en) * 2004-01-06 2005-12-27 Intel Corporation Apparatus and methods for an underfilled integrated circuit package
US9373559B2 (en) * 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
US10037900B1 (en) 2017-05-09 2018-07-31 Nxp B.V. Underfill stop using via bars in semiconductor packages
KR102477352B1 (ko) 2017-09-29 2022-12-15 삼성전자주식회사 반도체 패키지 및 이미지 센서
CN113113325A (zh) * 2021-04-08 2021-07-13 中国电子科技集团公司第二十四研究所 多芯片倒装焊三层封装结构的底填灌封方法
JP7594195B2 (ja) 2022-07-13 2024-12-04 日亜化学工業株式会社 発光装置の製造方法及び発光装置

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EP0340492A3 (en) 1988-05-02 1990-07-04 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
JPH0340458A (ja) 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US5321583A (en) 1992-12-02 1994-06-14 Intel Corporation Electrically conductive interposer and array package concept for interconnecting to a circuit board
US5539153A (en) 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
JP3233535B2 (ja) 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
JPH08153830A (ja) * 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
US5864178A (en) 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
EP0778616A3 (en) 1995-12-05 1999-03-31 Lucent Technologies Inc. Method of packaging devices with a gel medium confined by a rim member
US5766982A (en) 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
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US6016006A (en) 1996-06-24 2000-01-18 Intel Corporation Thermal grease insertion and retention
US5804771A (en) 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
JP2848357B2 (ja) 1996-10-02 1999-01-20 日本電気株式会社 半導体装置の実装方法およびその実装構造
JPH10112476A (ja) * 1996-10-04 1998-04-28 Fuji Xerox Co Ltd 半導体装置の製造方法
US5942805A (en) 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
JP2850894B2 (ja) * 1997-02-05 1999-01-27 日本電気株式会社 半導体実装方法
US5990552A (en) 1997-02-07 1999-11-23 Intel Corporation Apparatus for attaching a heat sink to the back side of a flip chip package
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JPH1154884A (ja) 1997-08-06 1999-02-26 Nec Corp 半導体装置の実装構造
JP3482115B2 (ja) 1997-10-13 2003-12-22 東レ・ダウコーニング・シリコーン株式会社 硬化性シリコーン組成物および電子部品
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US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US5998242A (en) 1997-10-27 1999-12-07 Lsi Logic Corporation Vacuum assisted underfill process and apparatus for semiconductor package fabrication
US5917702A (en) 1997-11-26 1999-06-29 Intel Corporation Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
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US5965937A (en) 1997-12-15 1999-10-12 Intel Corporation Thermal interface attach mechanism for electrical packages
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US5920120A (en) 1997-12-19 1999-07-06 Intel Corporation Assembly for dissipatating heat from a semiconductor chip wherein a stress on the semiconductor chip due to a thermally conductive member is partially relieved
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US6075712A (en) 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip

Also Published As

Publication number Publication date
US6331446B1 (en) 2001-12-18
KR20020005611A (ko) 2002-01-17
WO2000052752A2 (en) 2000-09-08
CN1354888A (zh) 2002-06-19
WO2000052752A3 (en) 2001-03-08
JP2002538625A (ja) 2002-11-12
CN1157782C (zh) 2004-07-14
MXPA01008692A (es) 2002-03-14
KR100443732B1 (ko) 2004-08-09

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase