CN1354888A - 利用加热到部分凝胶态的底层填料底层填充控制熔塌芯片连接(c4)集成电路封装的方法 - Google Patents

利用加热到部分凝胶态的底层填料底层填充控制熔塌芯片连接(c4)集成电路封装的方法 Download PDF

Info

Publication number
CN1354888A
CN1354888A CN00807121A CN00807121A CN1354888A CN 1354888 A CN1354888 A CN 1354888A CN 00807121 A CN00807121 A CN 00807121A CN 00807121 A CN00807121 A CN 00807121A CN 1354888 A CN1354888 A CN 1354888A
Authority
CN
China
Prior art keywords
substrate
integrated circuit
underfilling
attached
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN00807121A
Other languages
English (en)
Other versions
CN1157782C (zh
Inventor
D·库克
V·穆拉利
S·拉马林加姆
N·沃德拉哈利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1354888A publication Critical patent/CN1354888A/zh
Application granted granted Critical
Publication of CN1157782C publication Critical patent/CN1157782C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

在安装到基板上的集成电路的底层填充中的部分凝胶步骤。该工艺步骤包括分散第一底层填料,然后将该底层材料加热到部分凝胶态。部分凝胶步骤可以减少空洞的形成,改善水汽负载期间的粘附性能。

Description

利用加热到部分凝胶态的底层填料底层填充 控制熔塌芯片连接(C4)集成电路封装的方法
1.发明的背景
本发明涉及一种集成电路封装
2.背景信息
集成电路一般被组装到将焊接到印刷电路板上的封装中。图1示出了一种一般称为倒装芯片或C4封装的集成电路封装。集成电路1含有数个将焊接到基板3的上表面上的焊料凸点2。
基板3一般由热膨胀系数与集成电路不同的复合材料构成。封装温度的任何变化，都会引起集成电路1和基板3的不同膨胀。不同的膨胀会产生可能造成焊料凸点2龟裂的应力。该焊料凸点2运载集成电路1和基板3间的电流，所以凸点2的任何龟裂都会影响电路1的工作。
封装可以包括位于集成电路1和基板3间的底层填料4。该底层填料4一般是加强焊点可靠性和IC封装的热机械水汽稳定性的环氧树脂。
封装可以具有按两维阵列形式排列在集成电路1的底面上的数百焊料凸点2。环氧树脂4一般通过沿集成电路的一侧分散一条未固化环氧树脂材料线，加于焊料凸点界面上。然后，环氧树脂流到焊料凸点之间。环氧树脂4必须按能覆盖所有焊料凸点2的形式分散。
希望环氧树脂4仅在集成电路的一侧分散，以确保不在底层填料中形成气穴。气穴会减弱集成电路/基板界面的结构完整性。此外，底层填料4必须与基板3和集成电路1具有良好的粘附强度，以防止热和水汽负载期间的剥离。因此，环氧树脂4必须是处于可以在整个集成电路/基板界面之下流动的状态，同时具有良好的粘附特性的材料。
基板3一般由陶瓷材料构成。陶瓷材料对于批量生产来说较贵。因此，希望提供用于C4封装的有机基板。有机基板容易吸收会在底层填充过程中释放出来的水汽。底层填充工艺期间释放的水汽会在底层填料中产生空洞。有机基板还容易具有较陶瓷基板高的热膨胀系数，这样会在管芯、底层填料和焊料凸点中形成较大应力。环氧树脂中的较大应力会导致热负载期间发生龟裂，该龟裂会延伸到基板中，并会由于使金属线条断裂而造成封装失效。较大应力还会导致热负载期间管芯失效，并且提高对空气和水汽空洞的敏感性。尤其是对于具有较高凸点密度的封装来说，热负载期间，凸点会伸到空洞内。所以，希望提供一种能够利用有机基板的C4封装。
发明的概述
本发明的一个实施例是可以包括安装在基板上的集成电路的集成电路封装。该封装可以包括附着于集成电路和基板上的底层填料和密封底层填料的嵌条。
附图简介
图1是现有技术集成电路封装的侧视图；
图2是本发明的集成电路封装一个实施例的俯视图；
图3是该集成电路封装的放大侧视图；
图4是展示组装该集成电路封装的方法的示图。
发明的详细描述
利用参考数字更具体地参照各附图，图2和3示出了本发明的集成电路封装10的实施例。封装10可以包括具有第一表面14和第二相反表面16的基板12。集成电路18可以通过多个焊料凸点20附着于基板12的第一表面14上。焊料凸点20可以按两维阵列的方式排列于集成电路18上。可以利用一般称作控制熔塌芯片连接(C4)的方法，将焊料凸点20附着于集成电路18上和基板12上。
焊料凸点20可以在集成电路18和基板12之间运载电流。在一个实施例中，基板12可以包括有机介电材料。封装10可以包括多个附着到基板12的第二表面16的焊料球22。焊料球22可以回流，使封装10附着到印刷电路板(未示出)上。
基板12可以含有布线条、电源/接地面、通道等，它们将第一表面14上的焊料凸点20电连接到第二表面16上的焊料球22。集成电路18可以通过密封剂(未示出)密封。此外，封装10可以引入例如金属散热片或热沉等热元件(未示出)，用于散发集成电路18产生的热。
封装10可以包括附着于集成电路18和基板12上的第一底层填料24。封装10还可以包括附着到基板12和集成电路18上的第二底层填料26。第二底层填料26可以形成包围和密封IC的边缘和第一底层填料24的环形嵌条。第二材料26的密封作用可以防止水汽迁移、集成电路和第一底层填料龟裂。
第一底层填料24可以是产品名称为Semicoat 5230-JP由日本的Shin-Itsu制造的环氧树脂。Semicoat 5230-JP材料具有优异的流动性和粘附性。第二底层填料26可以是产品名称为Semicoat 122X由Shin-Itsu制造的酸酐环氧树脂(anhydride epoxy)。Semicoat122X材料的粘附性低于Semicoat 5230-JP，但更耐疲劳/龟裂。
图4示出了组装封装10的方法。首先，可以在烘箱28中烘焙基板12，去除基板材料中的水汽。较好是在高于其余底层填充工艺步骤的工艺温度的温度下烘焙基板12，以确保在随后的步骤中不会释放水汽。例如，可以在163℃的温度下烘焙基板12。
烘焙工艺后，可以将集成电路18安装到基板12上。一般通过回流焊料凸点20安装集成电路18。
可以在第一分散台30，沿集成电路18的一侧在基板12上分散第一底层填料24。第一底层填料24可以在灯芯作用下在集成电路18和基板12间流动。例如，可以在110-120℃的温度下，分散第一底层填料24。可以有一系列分散步骤，以充分填充集成电路18和基板12间的空间。
然后，可以通过烘箱32移动封装10，完成第一底层填充材料24的流动和部分凝胶化。例如，可以在烘箱32中，将该底层填料24加热到120-145℃的温度，以便使底层填料24部分凝胶化。部分凝胶化可以减少空洞的形成，改善集成电路18和底层填料24间的粘附性。粘附性的改善可以减少水汽的迁移和底层填料24与IC18间的剥离，以及底层填料24与基板的剥离。空洞形成的减少可以减少热负载期间凸点的伸出。可以在灯芯作用期间通过加热底层填料的烘箱32连续移动封装。在灯芯作用期间连续移动基板12，可以减少底层填充集成电路需要的时间，所以可以降低制造封装的成本。基板12可以在传送带(未示出)上通过烘箱在工作台30和34间移动。
可以在第二分散台34，沿集成电路18的四侧，在基板12上分散第二底层填充材料26。第二材料26可以按形成包封和密封第一材料24的嵌条的方式分散。例如，可以在约80-120℃的温度下，分散第二底层填料26。
第一和第二底层填充材料24和26可以固化为硬化状态。材料的固化可以在约150℃的温度下进行。底层填料24和26固化后，可以将焊料球22附着到基板12的第二表面16上。
尽管结合附图介绍和展示了特定的例示实施例，但应理解，这些实施例仅仅是例示，并非对该宽范围发明的限制，由于对所属领域的普通技术人员来说，可以产生各种其它改进，所以本发明不限于所展示和介绍的特定结构和设置。

Claims (15)

1.一种底层填充安装到基板上的集成电路的方法，包括以下步骤：
分散将附着于集成电路和基板上的第一底层填料；及
将第一底层填料加热到部分凝胶态。
2.根据权利要求1的方法，还包括分散将附着于集成和基板上的第二底层填料的步骤。
3.根据权利要求2的方法，其中第二底层填料按包围第一底层填料的方式分散。
4.根据权利要求1的方法，其中第一底层填料在集成电路和基板间流动。
5.根据权利要求1的方法，还包括在分散第一底层填料前加热基板的步骤。
6.根据权利要求5的方法，其中将基板加热到高于部分凝胶态的第一底层填料的温度的温度。
7.根据权利要求1的方法，还包括利用焊料凸点将集成电路安装于基板上的步骤。
8.根据权利要求7的方法，还包括将焊料球附着于基板上的步骤。
9.一种将集成电路安装和底层填充到基板上的方法，包括以下步骤：
烘焙基板；
在基板上安装集成电路；
分散将附着于集成电路和基板上的第一底层填料。
10.根据权利要求9的方法，还包括分散将附着于集成电路和基板上的第二底层填料的步骤。
11.根据权利要求9的方法，还包括利用焊料凸点将集成电路安装于基板上的步骤。
12.根据权利要求11的方法，还包括将焊料球附着于基板上的步骤。
13.一种将集成电路安装和底层填充到基板上的方法，包括以下步骤：
烘焙基板；
在基板上安装集成电路；
分散将附着于集成电路和基板上的第一底层填料；
将第一底层填料加热到部分凝胶态；
分散将附着于集成电路和基板上的第二底层填料。
14.根据权利要求13的方法，还包括利用焊料凸点将集成电路安装于基板上的步骤。
15.根据权利要求14的方法，还包括将焊料球附着于基板上的步骤。
CNB008071217A 1999-03-03 2000-02-08 利用加热到部分凝胶态的底层填料底层填充控制熔塌芯片连接(c4)集成电路封装的方法 Expired - Fee Related CN1157782C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/261,648 1999-03-03
US09/261,648 US6331446B1 (en) 1999-03-03 1999-03-03 Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state

Publications (2)

Publication Number Publication Date
CN1354888A true CN1354888A (zh) 2002-06-19
CN1157782C CN1157782C (zh) 2004-07-14

Family

ID=22994229

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB008071217A Expired - Fee Related CN1157782C (zh) 1999-03-03 2000-02-08 利用加热到部分凝胶态的底层填料底层填充控制熔塌芯片连接(c4)集成电路封装的方法

Country Status (7)

Country Link
US (1) US6331446B1 (zh)
JP (1) JP2002538625A (zh)
KR (1) KR100443732B1 (zh)
CN (1) CN1157782C (zh)
AU (1) AU2986200A (zh)
MX (1) MXPA01008692A (zh)
WO (1) WO2000052752A2 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6545869B2 (en) * 2001-01-17 2003-04-08 International Business Machines Corporation Adjusting fillet geometry to couple a heat spreader to a chip carrier
TW502422B (en) * 2001-06-07 2002-09-11 Ultra Tera Corp Method for encapsulating thin flip-chip-type semiconductor device
US20030129438A1 (en) * 2001-12-14 2003-07-10 Becker Kevin Harris Dual cure B-stageable adhesive for die attach
US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US7242097B2 (en) 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US6979600B2 (en) * 2004-01-06 2005-12-27 Intel Corporation Apparatus and methods for an underfilled integrated circuit package
US9373559B2 (en) * 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
US10037900B1 (en) 2017-05-09 2018-07-31 Nxp B.V. Underfill stop using via bars in semiconductor packages
KR102477352B1 (ko) 2017-09-29 2022-12-15 삼성전자주식회사 반도체 패키지 및 이미지 센서
CN113113325A (zh) * 2021-04-08 2021-07-13 中国电子科技集团公司第二十四研究所 多芯片倒装焊三层封装结构的底填灌封方法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322737A (en) 1979-11-20 1982-03-30 Intel Corporation Integrated circuit micropackaging
EP0340492A3 (en) 1988-05-02 1990-07-04 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
JPH0340458A (ja) 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US5321583A (en) 1992-12-02 1994-06-14 Intel Corporation Electrically conductive interposer and array package concept for interconnecting to a circuit board
US5539153A (en) 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
JP3233535B2 (ja) 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
JPH08153830A (ja) * 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
US5864178A (en) 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
EP0778616A3 (en) 1995-12-05 1999-03-31 Lucent Technologies Inc. Method of packaging devices with a gel medium confined by a rim member
US5766982A (en) 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
JP2891184B2 (ja) 1996-06-13 1999-05-17 日本電気株式会社 半導体装置及びその製造方法
US6016006A (en) 1996-06-24 2000-01-18 Intel Corporation Thermal grease insertion and retention
US5804771A (en) 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
JP2848357B2 (ja) 1996-10-02 1999-01-20 日本電気株式会社 半導体装置の実装方法およびその実装構造
JPH10112476A (ja) * 1996-10-04 1998-04-28 Fuji Xerox Co Ltd 半導体装置の製造方法
US5942805A (en) 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
JP2850894B2 (ja) * 1997-02-05 1999-01-27 日本電気株式会社 半導体実装方法
US5990552A (en) 1997-02-07 1999-11-23 Intel Corporation Apparatus for attaching a heat sink to the back side of a flip chip package
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5895229A (en) 1997-05-19 1999-04-20 Motorola, Inc. Microelectronic package including a polymer encapsulated die, and method for forming same
JPH1154884A (ja) 1997-08-06 1999-02-26 Nec Corp 半導体装置の実装構造
JP3482115B2 (ja) 1997-10-13 2003-12-22 東レ・ダウコーニング・シリコーン株式会社 硬化性シリコーン組成物および電子部品
US5919329A (en) 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US5998242A (en) 1997-10-27 1999-12-07 Lsi Logic Corporation Vacuum assisted underfill process and apparatus for semiconductor package fabrication
US5917702A (en) 1997-11-26 1999-06-29 Intel Corporation Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
US6049124A (en) 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US5936304A (en) 1997-12-10 1999-08-10 Intel Corporation C4 package die backside coating
US5965937A (en) 1997-12-15 1999-10-12 Intel Corporation Thermal interface attach mechanism for electrical packages
US5920120A (en) 1997-12-19 1999-07-06 Intel Corporation Assembly for dissipatating heat from a semiconductor chip wherein a stress on the semiconductor chip due to a thermally conductive member is partially relieved
US5991161A (en) 1997-12-19 1999-11-23 Intel Corporation Multi-chip land grid array carrier
US5953814A (en) 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
US6011301A (en) 1998-06-09 2000-01-04 Stmicroelectronics, Inc. Stress reduction for flip chip package
US6075712A (en) 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip

Also Published As

Publication number Publication date
WO2000052752A3 (en) 2001-03-08
JP2002538625A (ja) 2002-11-12
US6331446B1 (en) 2001-12-18
KR20020005611A (ko) 2002-01-17
KR100443732B1 (ko) 2004-08-09
WO2000052752A2 (en) 2000-09-08
AU2986200A (en) 2000-09-21
CN1157782C (zh) 2004-07-14
MXPA01008692A (es) 2002-03-14

Similar Documents

Publication Publication Date Title
CN1165979C (zh) 集成电路封装方法
CN1157782C (zh) 利用加热到部分凝胶态的底层填料底层填充控制熔塌芯片连接(c4)集成电路封装的方法
US7900809B2 (en) Solder interconnection array with optimal mechanical integrity
EP1186212B1 (en) Integrated circuit package having a substrate vent hole
US5414928A (en) Method of making an electronic package assembly with protective encapsulant material
KR19990006293A (ko) 플립칩과 볼 그리드 어레이 (bga)를 상호 접속시키는 방법
US7141448B2 (en) Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials
US6528345B1 (en) Process line for underfilling a controlled collapse
KR100498675B1 (ko) 두 가지 다른 하부 충전 재료를 갖는 붕괴 제어형 칩접속(ｃ4) 집적회로 패키지
JPH1098077A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20040714

Termination date: 20150208

EXPY Termination of patent right or utility model