JP2002538624A - 制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス・ライン - Google Patents

制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス・ライン

Info

Publication number
JP2002538624A
JP2002538624A JP2000603088A JP2000603088A JP2002538624A JP 2002538624 A JP2002538624 A JP 2002538624A JP 2000603088 A JP2000603088 A JP 2000603088A JP 2000603088 A JP2000603088 A JP 2000603088A JP 2002538624 A JP2002538624 A JP 2002538624A
Authority
JP
Japan
Prior art keywords
substrate
underfill material
integrated circuit
package
process line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000603088A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002538624A5 (https=
Inventor
クック，デュエーン
ラマリンガム，スレシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2002538624A publication Critical patent/JP2002538624A/ja
Publication of JP2002538624A5 publication Critical patent/JP2002538624A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2000603088A 1999-03-03 2000-02-08 制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス・ライン Pending JP2002538624A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/262,132 US6528345B1 (en) 1999-03-03 1999-03-03 Process line for underfilling a controlled collapse
US09/262,132 1999-03-03
PCT/US2000/003243 WO2000052751A1 (en) 1999-03-03 2000-02-08 A process line for underfilling a controlled collapse chip connection (c4) integrated circuit package

Publications (2)

Publication Number Publication Date
JP2002538624A true JP2002538624A (ja) 2002-11-12
JP2002538624A5 JP2002538624A5 (https=) 2007-03-15

Family

ID=22996282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000603088A Pending JP2002538624A (ja) 1999-03-03 2000-02-08 制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス・ライン

Country Status (7)

Country Link
US (1) US6528345B1 (https=)
JP (1) JP2002538624A (https=)
KR (1) KR100438991B1 (https=)
CN (1) CN1171296C (https=)
AU (1) AU2986100A (https=)
MX (1) MXPA01008581A (https=)
WO (1) WO2000052751A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12507513B2 (en) 2022-07-13 2025-12-23 Nichia Corporation Method for manufacturing light-emitting device, and light-emitting device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US7238550B2 (en) * 2002-02-26 2007-07-03 Tandon Group Ltd. Methods and apparatus for fabricating Chip-on-Board modules
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050121310A1 (en) * 2003-12-03 2005-06-09 Intel Corporation Method and substrate to control flow of underfill
JP5262045B2 (ja) * 2007-09-27 2013-08-14 富士通セミコンダクター株式会社 電極の形成方法及び半導体装置の製造方法
US7915732B2 (en) * 2008-06-30 2011-03-29 International Business Mahines Corporation Production of integrated circuit chip packages prohibiting formation of micro solder balls

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153830A (ja) * 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322737A (en) 1979-11-20 1982-03-30 Intel Corporation Integrated circuit micropackaging
JPS63239827A (ja) 1987-03-27 1988-10-05 Hitachi Ltd 半導体装置
EP0340492A3 (en) * 1988-05-02 1990-07-04 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
JPH0256941A (ja) 1988-08-20 1990-02-26 Matsushita Electric Works Ltd 半導体素子の封止方法
JPH0340458A (ja) 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH0639563B2 (ja) 1989-12-15 1994-05-25 株式会社日立製作所 半導体装置の製法
US5371325A (en) 1992-10-30 1994-12-06 At&T Corp. Insulation system for magnetic devices
US5321583A (en) 1992-12-02 1994-06-14 Intel Corporation Electrically conductive interposer and array package concept for interconnecting to a circuit board
US5371328A (en) 1993-08-20 1994-12-06 International Business Machines Corporation Component rework
JP2774436B2 (ja) 1993-09-07 1998-07-09 リンナイ株式会社 多孔質体
US5539153A (en) 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
JP3233535B2 (ja) 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
US5864178A (en) 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5811317A (en) 1995-08-25 1998-09-22 Texas Instruments Incorporated Process for reflow bonding a semiconductor die to a substrate and the product produced by the product
EP0778616A3 (en) 1995-12-05 1999-03-31 Lucent Technologies Inc. Method of packaging devices with a gel medium confined by a rim member
US5766982A (en) 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
JP3235454B2 (ja) 1996-03-29 2001-12-04 松下電器産業株式会社 電子部品の接合方法
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
US5821456A (en) 1996-05-01 1998-10-13 Motorola, Inc. Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same
JP2891184B2 (ja) * 1996-06-13 1999-05-17 日本電気株式会社 半導体装置及びその製造方法
JPH1055832A (ja) 1996-08-08 1998-02-24 Yazaki Corp 圧接端子
US5804771A (en) 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
JP2848357B2 (ja) 1996-10-02 1999-01-20 日本電気株式会社 半導体装置の実装方法およびその実装構造
US5942805A (en) 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US5990552A (en) 1997-02-07 1999-11-23 Intel Corporation Apparatus for attaching a heat sink to the back side of a flip chip package
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US6104093A (en) 1997-04-24 2000-08-15 International Business Machines Corporation Thermally enhanced and mechanically balanced flip chip package and method of forming
JPH1154884A (ja) 1997-08-06 1999-02-26 Nec Corp 半導体装置の実装構造
US5919329A (en) 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US5998242A (en) 1997-10-27 1999-12-07 Lsi Logic Corporation Vacuum assisted underfill process and apparatus for semiconductor package fabrication
US5917702A (en) 1997-11-26 1999-06-29 Intel Corporation Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
US5936304A (en) 1997-12-10 1999-08-10 Intel Corporation C4 package die backside coating
US6049124A (en) 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US5965937A (en) 1997-12-15 1999-10-12 Intel Corporation Thermal interface attach mechanism for electrical packages
US5991161A (en) 1997-12-19 1999-11-23 Intel Corporation Multi-chip land grid array carrier
US5920120A (en) 1997-12-19 1999-07-06 Intel Corporation Assembly for dissipatating heat from a semiconductor chip wherein a stress on the semiconductor chip due to a thermally conductive member is partially relieved
US6201301B1 (en) 1998-01-21 2001-03-13 Lsi Logic Corporation Low cost thermally enhanced flip chip BGA
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
US6057381A (en) * 1998-07-02 2000-05-02 National Starch And Chemical Investment Holding Corporation Method of making an electronic component using reworkable underfill encapsulants
US6238948B1 (en) 1999-03-03 2001-05-29 Intel Corporation Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153830A (ja) * 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12507513B2 (en) 2022-07-13 2025-12-23 Nichia Corporation Method for manufacturing light-emitting device, and light-emitting device

Also Published As

Publication number Publication date
WO2000052751A1 (en) 2000-09-08
MXPA01008581A (es) 2002-04-24
KR100438991B1 (ko) 2004-07-02
US6528345B1 (en) 2003-03-04
KR20020005612A (ko) 2002-01-17
AU2986100A (en) 2000-09-21
CN1171296C (zh) 2004-10-13
CN1344424A (zh) 2002-04-10

Similar Documents

Publication Publication Date Title
JP2002540593A (ja) アンダーフィル材料を封止するフィラーを有する制御崩壊チップ接続（ｃ４）集積回路パッケージ
US9263426B2 (en) PoP structure with electrically insulating material between packages
JP2002538626A (ja) ２つの異なるアンダーフィル材料を有する制御崩壊チップ接続（ｃ４）集積回路パッケージ
JP2002538625A (ja) 部分的にゲル状態に加熱されたアンダーフィル材料を有する制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス
US7663254B2 (en) Semiconductor apparatus and method of manufacturing the same
US6225144B1 (en) Method and machine for underfilling an assembly to form a semiconductor package
JP2002538624A (ja) 制御崩壊チップ接続（ｃ４）集積回路パッケージをアンダーフィルするプロセス・ライン
JPH1187424A (ja) 半導体装置およびその製造方法
CN101989554B (zh) 封装结构及封装工艺
JPH10209591A (ja) 配線基板
JP2004063524A (ja) 実装装置及びその実装方法若しくはプリント配線基板
KR100498675B1 (ko) 두 가지 다른 하부 충전 재료를 갖는 붕괴 제어형 칩접속(ｃ4) 집적회로 패키지
JP2002016104A (ja) 半導体装置の実装方法および半導体装置実装体の製造方法
JPH06244244A (ja) 半導体装置実装用基板
JPH08153751A (ja) 電子デバイス組立体およびその製造方法
JPH09153514A (ja) 半導体ユニット及び半導体素子の実装方法
JP2001237270A (ja) 半導体素子の実装方法とその実装体
JP2003264259A (ja) 半導体装置及びその実装方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070123

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070123

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090820

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090908

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091208

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100108

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100706