MXPA01008581A - Una linea de proceso para subrellenar un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4). - Google Patents

Una linea de proceso para subrellenar un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4).

Info

Publication number
MXPA01008581A
MXPA01008581A MXPA01008581A MXPA01008581A MXPA01008581A MX PA01008581 A MXPA01008581 A MX PA01008581A MX PA01008581 A MXPA01008581 A MX PA01008581A MX PA01008581 A MXPA01008581 A MX PA01008581A MX PA01008581 A MXPA01008581 A MX PA01008581A
Authority
MX
Mexico
Prior art keywords
substrate
sub
integrated circuit
filler material
process according
Prior art date
Application number
MXPA01008581A
Other languages
English (en)
Spanish (es)
Inventor
Suresh Ramalingam
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of MXPA01008581A publication Critical patent/MXPA01008581A/es

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
MXPA01008581A 1999-03-03 2000-02-08 Una linea de proceso para subrellenar un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4). MXPA01008581A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/262,132 US6528345B1 (en) 1999-03-03 1999-03-03 Process line for underfilling a controlled collapse
PCT/US2000/003243 WO2000052751A1 (en) 1999-03-03 2000-02-08 A process line for underfilling a controlled collapse chip connection (c4) integrated circuit package

Publications (1)

Publication Number Publication Date
MXPA01008581A true MXPA01008581A (es) 2002-04-24

Family

ID=22996282

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA01008581A MXPA01008581A (es) 1999-03-03 2000-02-08 Una linea de proceso para subrellenar un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4).

Country Status (7)

Country Link
US (1) US6528345B1 (https=)
JP (1) JP2002538624A (https=)
KR (1) KR100438991B1 (https=)
CN (1) CN1171296C (https=)
AU (1) AU2986100A (https=)
MX (1) MXPA01008581A (https=)
WO (1) WO2000052751A1 (https=)

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US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US7238550B2 (en) * 2002-02-26 2007-07-03 Tandon Group Ltd. Methods and apparatus for fabricating Chip-on-Board modules
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050121310A1 (en) * 2003-12-03 2005-06-09 Intel Corporation Method and substrate to control flow of underfill
JP5262045B2 (ja) * 2007-09-27 2013-08-14 富士通セミコンダクター株式会社 電極の形成方法及び半導体装置の製造方法
US7915732B2 (en) * 2008-06-30 2011-03-29 International Business Mahines Corporation Production of integrated circuit chip packages prohibiting formation of micro solder balls
JP7594195B2 (ja) 2022-07-13 2024-12-04 日亜化学工業株式会社 発光装置の製造方法及び発光装置

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US5321583A (en) 1992-12-02 1994-06-14 Intel Corporation Electrically conductive interposer and array package concept for interconnecting to a circuit board
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JP3233535B2 (ja) 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
JPH08153830A (ja) 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
US5864178A (en) 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
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US5942805A (en) 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
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Also Published As

Publication number Publication date
JP2002538624A (ja) 2002-11-12
WO2000052751A1 (en) 2000-09-08
KR100438991B1 (ko) 2004-07-02
US6528345B1 (en) 2003-03-04
KR20020005612A (ko) 2002-01-17
AU2986100A (en) 2000-09-21
CN1171296C (zh) 2004-10-13
CN1344424A (zh) 2002-04-10

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Legal Events

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FG Grant or registration
MM Annulment or lapse due to non-payment of fees