KR100438991B1 - 붕괴 제어형 칩 접속(ｃ4) 집적회로 패키지의 하부를충전하는 프로세스 라인 - Google Patents

붕괴 제어형 칩 접속(ｃ4) 집적회로 패키지의 하부를충전하는 프로세스 라인 Download PDF

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Publication number
KR100438991B1
KR100438991B1 KR10-2001-7011229A KR20017011229A KR100438991B1 KR 100438991 B1 KR100438991 B1 KR 100438991B1 KR 20017011229 A KR20017011229 A KR 20017011229A KR 100438991 B1 KR100438991 B1 KR 100438991B1
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KR
South Korea
Prior art keywords
substrate
integrated circuit
temperature range
fill material
filling material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2001-7011229A
Other languages
English (en)
Korean (ko)
Other versions
KR20020005612A (ko
Inventor
쿠크듀언
라말링감수레쉬
Original Assignee
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20020005612A publication Critical patent/KR20020005612A/ko
Application granted granted Critical
Publication of KR100438991B1 publication Critical patent/KR100438991B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR10-2001-7011229A 1999-03-03 2000-02-08 붕괴 제어형 칩 접속(ｃ4) 집적회로 패키지의 하부를충전하는 프로세스 라인 Expired - Fee Related KR100438991B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/262,132 US6528345B1 (en) 1999-03-03 1999-03-03 Process line for underfilling a controlled collapse
US09/262,132 1999-03-03
PCT/US2000/003243 WO2000052751A1 (en) 1999-03-03 2000-02-08 A process line for underfilling a controlled collapse chip connection (c4) integrated circuit package

Publications (2)

Publication Number Publication Date
KR20020005612A KR20020005612A (ko) 2002-01-17
KR100438991B1 true KR100438991B1 (ko) 2004-07-02

Family

ID=22996282

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-7011229A Expired - Fee Related KR100438991B1 (ko) 1999-03-03 2000-02-08 붕괴 제어형 칩 접속(ｃ4) 집적회로 패키지의 하부를충전하는 프로세스 라인

Country Status (7)

Country Link
US (1) US6528345B1 (https=)
JP (1) JP2002538624A (https=)
KR (1) KR100438991B1 (https=)
CN (1) CN1171296C (https=)
AU (1) AU2986100A (https=)
MX (1) MXPA01008581A (https=)
WO (1) WO2000052751A1 (https=)

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US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US7238550B2 (en) * 2002-02-26 2007-07-03 Tandon Group Ltd. Methods and apparatus for fabricating Chip-on-Board modules
US6798806B1 (en) * 2002-09-03 2004-09-28 Finisar Corporation Hybrid mirror VCSELs
US7026376B2 (en) * 2003-06-30 2006-04-11 Intel Corporation Fluxing agent for underfill materials
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050121310A1 (en) * 2003-12-03 2005-06-09 Intel Corporation Method and substrate to control flow of underfill
JP5262045B2 (ja) * 2007-09-27 2013-08-14 富士通セミコンダクター株式会社 電極の形成方法及び半導体装置の製造方法
US7915732B2 (en) * 2008-06-30 2011-03-29 International Business Mahines Corporation Production of integrated circuit chip packages prohibiting formation of micro solder balls
JP7594195B2 (ja) 2022-07-13 2024-12-04 日亜化学工業株式会社 発光装置の製造方法及び発光装置

Citations (2)

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EP0340492A2 (en) * 1988-05-02 1989-11-08 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability

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JPH0256941A (ja) 1988-08-20 1990-02-26 Matsushita Electric Works Ltd 半導体素子の封止方法
JPH0340458A (ja) 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH0639563B2 (ja) 1989-12-15 1994-05-25 株式会社日立製作所 半導体装置の製法
US5371325A (en) 1992-10-30 1994-12-06 At&T Corp. Insulation system for magnetic devices
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JP3233535B2 (ja) 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
JPH08153830A (ja) 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
US5864178A (en) 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
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JP3235454B2 (ja) 1996-03-29 2001-12-04 松下電器産業株式会社 電子部品の接合方法
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
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JP2891184B2 (ja) * 1996-06-13 1999-05-17 日本電気株式会社 半導体装置及びその製造方法
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Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
EP0340492A2 (en) * 1988-05-02 1989-11-08 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability

Also Published As

Publication number Publication date
JP2002538624A (ja) 2002-11-12
WO2000052751A1 (en) 2000-09-08
MXPA01008581A (es) 2002-04-24
US6528345B1 (en) 2003-03-04
KR20020005612A (ko) 2002-01-17
AU2986100A (en) 2000-09-21
CN1171296C (zh) 2004-10-13
CN1344424A (zh) 2002-04-10

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